PDF SI53323 Data sheet ( Hoja de datos )

Número de pieza	SI53323
Descripción	1:4 LOW-JITTER LVPECL CLOCK BUFFER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si53323 1:4 LOW-JITTER LVPECL CLOCK BUFFER WITH 2:1 INPUT MUX Features  4 LVPECL outputs  VDD: 2.5 / 3.3 V  Ultra-low additive jitter: 55 fs rms  Small size: 16-QFN (3 mm x  Wide frequency range: dc to 3 mm) 1250 MHz  RoHS compliant, Pb-free  2:1 input mux  Industrial temperature range:  Universal input stage accepts –40 to +85 °C differential or LVCMOS clock Applications  High-speed clock distribution  Storage  Ethernet switch/router  Telecom  Optical Transport Network (OTN)  Industrial  SONET/SDH  Servers  PCI Express Gen 1/2/3  Backplane clock distribution Description The Si53323 is an ultra-low-jitter four-output LVPECL buffer. The Si53323 features a 2:1 input mux, making it ideal for redundant clocking applications. Utilizing Silicon Laboratories’ advanced fan-out clock technology, the Si53323 guarantees low additive jitter, low skew, and low propagation delay variability from dc to 1250 MHz. The Si53323 features minimal cross-talk and excellent supply noise rejection, simplifying low-jitter clock distribution in noisy environments. Functional Block Diagram Ordering Information: See page 18. Pin Assignments GND CLK_SEL CLK1 CLK1 1 2 3 4 EXPOSED GND PAD 12 Q1 11 Q1 10 Q0 9 Q0 Patents pending VDD CLK0 CLK0 CLK1 CLK1 CLK_SEL Power Supply Filtering Switching Logic Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Rev. 1.0 7/15 Copyright © 2015 by Silicon Laboratories Si53323 1 page Si53323 Table 6. Additive Jitter, Differential Clock Input VDD Input1,2 Output Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Differential Clock Format 20%-80% Slew Rate (V/ns) 3.3 725 Differential 0.15 0.637 LVPECL 3.3 156.25 Differential 0.5 0.458 LVPECL 2.5 725 Differential 0.15 0.637 LVPECL 2.5 156.25 Differential 0.5 0.458 LVPECL Typ 55 160 55 145 Max 95 185 95 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. Table 7. Additive Jitter, Single-Ended Clock Input VDD Input1,2 Output Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) SE 20%-80% Slew Rate (V/ns) Clock Format 3.3 156.25 Single-ended 2.18 1 LVPECL 2.5 156.25 Single-ended 2.18 1 LVPECL Typ 160 145 Max 185 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. CLK SYNTH SMA103A PSPL 5310A Balun Si533xx DUT CLKx /CLKx 50 50 PSPL 5310A Balun AG E5052 Phase Noise Analyzer 50ohm Figure 1. Differential Measurement Method Using a Balun Rev. 1.0 5 5 Page 2.5. AC Timing Waveforms CLK TPHL VPP/2 Q VPP/2 TPLH Propagation Delay Si53323 TSK QN VPP/2 QM VPP/2 TSK Output-Output Skew TF Q Q80% VPP 20% VPP 80% VPP 20% VPP TR Rise/Fall Time Figure 7. AC Waveforms Rev. 1.0 11 11 Page

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