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PDF SI53320 Data sheet ( Hoja de datos )
| Número de pieza | SI53320 | |
| Descripción | 1:5 LOW JITTER LVPECL CLOCK BUFFER | |
| Fabricantes | Silicon Laboratories | |
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Si53320
1:5 LOW JITTER LVPECL CLOCK BUFFER
WITH 2:1 INPUT MUX
Features
5 LVPECL outputs
20-TSSOP
Ultra-low additive jitter: 100 fs rms RoHS compliant, Pb-free
Wide frequency range: 1 to 725 MHz Industrial temperature range:
Input compatible with LVPECL,
–40 to +85 °C
LVDS, CML, HCSL, LVCMOS
Footprint-compatible with
2:1 mux
MC100LVEP14, SY100EP14U
Glitchless input clock switching
Synchronous output enable
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53320 is an ultra low jitter five output LVPECL buffer with synchronous OE.
Outputs are enabled/disabled in a low state, ensuring runt pulses are not created
when the device is enabled/disabled. The Si53320 features a 2:1 input mux,
making it ideal for redundant clocking applications. The Si53320 utilizes Silicon
Laboratories’ advanced CMOS technology to fanout clocks from 1 to 725 MHz
with guaranteed low additive jitter, low skew, and low propagation delay variability.
The Si53320 features minimal cross-talk and provides superior supply noise
rejection, simplifying low jitter clock distribution in noisy environments.
Functional Block Diagram
Ordering Information:
See page 20.
Pin Assignments
Q0 1
Q0 2
Q1 3
Q1 4
Q2 5
Q2 6
Q3 7
Q3 8
20 VDD
19 OE
18 VDD
17 CLK1
16 CLK1
15 NC
14 CLK0
13 CLK0
VDD
Power
Supply
Filtering
Q4 9
Q4 10
12 CLK_SEL
11 GND
Q0
CLK0
CLK0
0
Q0
Q1 Patents pending
Q1
Q2
CLK1
CLK1
CLK_SEL
1
Switching
Logic
Q2
Q3
Q3
Q4
Q4
GND
OE
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si53320
1 page  
Si53320
Table 5. AC Characteristics (Continued)
(VDD = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Power Supply Noise
Rejection3
Symbol
PSRR
Test Condition
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
Min Typ Max Unit
— –67.5 —
dBc
— –62.5 —
dBc
— –60 — dBc
1 MHz sinusoidal noise
— –55 — dBc
Notes:
1. Output-to-output skew specified for outputs with identical configuration.
2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDD (3.3 V = 100 mVPP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
Table 6. Additive Jitter, Differential Clock Input
VDD
Input1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)3
Freq
(MHz)
Clock Format
Amplitude
VIN
(Single-Ended,
Peak-to-Peak)
Differential Clock Format
20%-80% Slew
Rate (V/ns)
3.3 725 Differential
0.15
0.637
LVPECL
3.3 156.25 Differential
0.5
0.458
LVPECL
2.5 725 Differential
0.15
0.637
LVPECL
2.5 156.25 Differential
0.5
0.458
LVPECL
Typ
45
160
45
145
Max
65
185
65
185
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Rev. 1.0
5
5 Page 
Si53320
2.4. Synchronous Output Enable
The Si53320 features a synchronous output enable (disable) feature. The output enable pin is sampled and
synchronized to the falling edge of the input clock. This feature prevents runt pulses from being generated when
the outputs are enabled or disabled.
When OE is high, Q is held low and Q is held high. The device features an internal pull-down resistor, so the
outputs are enabled when the output enable pin is unconnected. See Table 5, “AC Characteristics,” on page 4 for
output enable and output disable times.
2.5. Input Mux and Output Enable Logic
The Si53320 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 12. Input Mux and Output Enable Logic
CLK_SEL
L
CLK0
L
CLK1
X
OE1
L
Q2
L
L HXLH
HXLLL
H XHLH
X X X H L3
Notes:
1. Output enable active low
2. On the next negative transition of CLK0 or CLK1.
3. Q=low, Q=high
Rev. 1.0
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet SI53320.PDF ] | |
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