PDF SI53321 Data sheet ( Hoja de datos )

Número de pieza	SI53321
Descripción	1:10 LOW JITTER LVPECL CLOCK BUFFER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si53321 1:10 LOW JITTER LVPECL CLOCK BUFFER WITH 2:1 INPUT MUX (<1.25 GHZ) Features  10 LVPECL outputs  RoHS compliant, Pb-free  Ultra-low additive jitter: 45 fs rms typ  32-QFN, 32-eLQFP  Wide frequency range: dc to  Industrial temperature range: 1.25 GHz –40 to +85°C  Input compatible with LVPECL,  Footprint-compatible with LVDS, CML, HCSL, LVCMOS MC100LVEP111, CDCLVP111,  2:1 input mux  Low output-output skew: 25 ps (typ) MAX9311, ICS853S111BI, ICS85310-1 Applications  High-speed clock distribution  Ethernet switch/router  Optical Transport Network (OTN)  SONET/SDH  PCI Express Gen 1/2/3  Storage  Telecom  Industrial  Servers  Backplane clock distribution Ordering Information: See page 19. Pin Assignments (Top View) Description The Si53321 is an ultra-low jitter ten output differential buffer. The Si53321 features a 2:1 input mux, making it ideal for redundant clocking applications. The Si53321 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53321 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Functional Block Diagram VDD CLK_SEL CLK0 CLK0 NC CLK1 CLK1 GND 32 31 30 29 28 27 26 25 1 24 2 23 3 22 4 Exposed 21 5 GND Pad 20 6 19 7 18 8 9 17 10 11 12 13 14 15 16 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 VDD Power Supply Filtering CLK0 CLK0 CLK1 CLK1 CLK_SEL 0 1 GND Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 32 31 30 29 28 27 26 25 VDD 1 24 Q3 CLK_SEL 2 23 Q3 CLK0 3 CLK0 4 NC 5 Exposed GND Pad 22 Q4 21 Q4 20 Q5 CLK1 6 19 Q5 CLK1 7 18 Q6 GND 8 17 Q6 9 10 11 12 13 14 15 16 Patents pending Rev. 1.0 4/15 Copyright © 2015 by Silicon Laboratories Si53321 1 page Si53321 Table 6. Additive Jitter, Differential Clock Input VDD Input1,2 Output Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Differential Clock Format 20%-80% Slew Rate (V/ns) 3.3 725 Differential 0.15 0.637 LVPECL 3.3 156.25 Differential 0.5 0.458 LVPECL 2.5 725 Differential 0.15 0.637 LVPECL 2.5 156.25 Differential 0.5 0.458 LVPECL Typ 45 160 45 145 Max 65 185 65 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. Table 7. Additive Jitter, Single-Ended Clock Input VDD Input1,2 Output Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) SE 20%-80% Slew Rate (V/ns) Clock Format 3.3 156.25 Single-ended 2.18 1 LVPECL 2.5 156.25 Single-ended 2.18 1 LVPECL Typ 160 145 Max 185 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. CLK SYNTH SMA103A PSPL 5310A Balun Si533xx DUT CLKx /CLKx 50 50 PSPL 5310A Balun AG E5052 Phase Noise Analyzer 50ohm Figure 1. Differential Measurement Method Using a Balun Rev. 1.0 5 5 Page 2.5. AC Timing Waveforms CLK TPHL VPP/2 Q VPP/2 TPLH Propagation Delay Si53321 TSK QN VPP/2 QM VPP/2 TSK Output-Output Skew TF Q Q80% VPP 20% VPP 80% VPP 20% VPP TR Rise/Fall Time Figure 7. AC Waveforms Rev. 1.0 11 11 Page

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