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PDF SI53322 Data sheet ( Hoja de datos )
| Número de pieza | SI53322 | |
| Descripción | 1:2 LOW JITTER LVPECL CLOCK BUFFER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si53322
1:2 LOW JITTER LVPECL CLOCK BUFFER (>1.25 GHZ)
Features
2 LVPECL outputs
VDD: 2.5 / 3.3 V
Ultra-low additive jitter: 55 fs rms Small size: 16-QFN (3 mm x
Wide frequency range: dc to
3 mm)
1250 MHz
RoHS compliant, Pb-free
Universal input stage accepts Industrial temperature range:
differential or LVCMOS clock
–40 to +85 °C
Applications
High-speed clock distribution Storage
Ethernet switch/router
Telecom
Optical Transport Network (OTN) Industrial
SONET/SDH
Servers
PCI Express Gen 1/2/3
Backplane clock distribution
Description
The Si53322 is an ultra-low-jitter two-output LVPECL buffer. Utilizing
Silicon Laboratories’ advanced fan-out clock technology, the Si53322
guarantees low additive jitter, low skew, and low propagation delay
variability from dc to 1250 MHz.
The Si53322 features minimal cross-talk and excellent supply noise
rejection, simplifying low-jitter clock distribution in noisy environments.
Functional Block Diagram
Ordering Information:
See page 17.
Pin Assignments
GND 1
NC 2
NC 3
NC 4
EXPOSED
GND
PAD
12 Q1
11 Q1
10 Q0
9 Q0
VDD
CLK
CLK
Power
Supply
Filtering
Patents pending
Q0
Q0
Q1
Q1
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si53322
1 page  
Si53322
Table 6. Additive Jitter, Differential Clock Input
VDD
Input1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)3
Freq
(MHz)
Clock Format
Amplitude
VIN
(Single-Ended,
Peak-to-Peak)
Differential Clock Format
20%-80% Slew
Rate (V/ns)
Typ
Max
3.3 725 Differential
0.15
0.637
LVPECL
55 95
3.3 156.25 Differential
0.5
0.458
LVPECL
160 185
2.5 725 Differential
0.15
0.637
LVPECL
55 95
2.5 156.25 Differential
0.5
0.458
LVPECL
145 185
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Table 7. Additive Jitter, Single-Ended Clock Input
VDD
Input1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)3
Freq
(MHz)
Clock Format
Amplitude
VIN
(single-ended,
peak to peak)
SE 20%-80%
Slew Rate
(V/ns)
Clock Format
Typ
Max
3.3 156.25 Single-ended
2.18
1 LVPECL 160 185
2.5 156.25 Single-ended
2.18
1 LVPECL 145 185
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
CLK SYNTH
SMA103A
PSPL 5310A
Balun
Si533xx
DUT
CLKx
/CLKx
50
50
PSPL 5310A
Balun
AG E5052 Phase Noise
Analyzer
50ohm
Figure 1. Differential Measurement Method Using a Balun
Rev. 1.0
5
5 Page 
2.4. AC Timing Waveforms
CLK
TPHL
VPP/2
Q VPP/2
TPLH
Propagation Delay
Si53322
TSK
QN VPP/2
QM
VPP/2
TSK
Output-Output Skew
TF
Q Q80% VPP
20% VPP
80% VPP
20% VPP
TR
Rise/Fall Time
Figure 7. AC Waveforms
Rev. 1.0
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet SI53322.PDF ] | |
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