PDF CY2302 Data sheet ( Hoja de datos )

Número de pieza	CY2302
Descripción	Frequency Multiplier and Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! Features ■ 90 ps typical jitter OUT2 ■ 200 ps typical jitter OUT1 ■ 65 ps typical output-to-output skew ■ 90 ps typical propagation delay ■ Voltage range: 3.3 V±5%, or 5 V±10% ■ Output frequency range: 5 MHz to 133 MHz ■ Two outputs ■ Configuration options allow various multiplications of the reference frequency—refer to Table 1 to determine the specific option which meets your multiplication needs ■ Available in 8-pin SOIC package CY2302 Frequency Multiplier and Zero Delay Buffer Table 1. Configuration Options FBIN OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT2 FS0 FS1 OUT1 0 0 2 X REF 1 0 4 X REF 01 REF 1 1 8 X REF 0 0 4 X REF 1 0 8 X REF 0 1 2 X REF 1 1 16 X REF OUT2 REF 2 X REF REF/2 4 X REF 2 X REF 4 X REF REF 8 X REF Logic Block Diagram FBIN External feedback connection to OUT1 or OUT2, not both FS0 FS1 ÷Q IN Reference Input Phase Detector Charge Pump Loop Filter Output Buffer VCO ÷2 Output Buffer OUT1 OUT2 Cypress Semiconductor Corporation • 198 Champion Court Document #: 38-07154 Rev. E • San Jose, CA 95134-1709 • 408-943-2600 Revised March 24, 2011 [+] Feedback 1 page CY2302 AC Electrical Characteristics TA = 0°C to +70°C or –40° to 85°C, VDD = 3.3V ±5%[3] Parameter Description Test Condition Min Typ Max fIN Input Frequency[1] — 5 — 133 fOUT Output Frequency OUT1 15-pF load 10 — 133 tR Output Rise Time 0.8 V to 2.0 V, 15-pF load — — 3.5 tF Output Fall Time 2.0 V to 0.8 V, 15-pF load — — 2.5 tICLKR Input Clock Rise Time[2] — — — 10 tICLKF Input Clock Fall Time[2] — — — 10 tD Duty Cycle 15-pF load[5] 40 50 60 tLOCK PLL Lock Time Power supply stable — — 1.0 tJC Jitter, Cycle-to-Cycle OUT1, fOUT >30 MHz — 200 300 tDC Die Out Time[6] OUT2, fOUT >30 MHz — 90 300 — 100 — — tSKEW tPD Output-output Skew[4] Propagation Delay[4] — — — –350 65 90 250 350 AC Electrical Characteristics TA = 0°C to +70°C or –40° to 85°C, VDD = 5.0V ±10%[3] Parameter Description Test Condition Min Typ Max fIN Input Frequency[1] — 5 — 133 fOUT Output Frequency OUT1 15-pF load 10 — 133 tR Output Rise Time 0.8 V to 2.0 V, 15-pF load — — 2.5 tF Output Fall Time 2.0 V to 0.8 V, 15-pF load — — 1.5 tICLKR Input Clock Rise Time[2] — — — 10 tICLKF Input Clock Fall Time[2] — — — 10 tD Duty Cycle 15-pF load[5, 7] 40 50 60 tLOCK PLL Lock Time Power supply stable — — 1.0 tJC Jitter, Cycle-to-Cycle OUT1, fOUT >30 MHz — 200 300 tDC Die out time[6] OUT2, fOUT >30 MHz — 90 300 — 100 — — tSKEW tPD Output-output Skew[4] Propagation Delay[4] — — — –350 65 90 250 350 Notes 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time degrades skew and jitter performance. 3. All AC specifications are measured with a 50 transmission line, load terminated with 50  to 1.4 V. 4. Skew is measured at 1.4 V on rising edges. 5. Duty cycle is measured at 1.4 V. 6. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to <16 MHz. 7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case. Unit MHz MHz ns ns ns ns % ms ps ps Clock Cycles ps ps Unit MHz MHz ns ns ns ns % ms ps ps Clock cycles ps ps Document #: 38-07154 Rev. E Page 5 of 9 [+] Feedback 5 Page

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