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PDF CY2303 Data sheet ( Hoja de datos )
| Número de pieza | CY2303 | |
| Descripción | Phase-Aligned Clock Multiplier | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2303
Phase-Aligned Clock Multiplier
Phase-Aligned Clock Multiplier
Features
■ 3-Multiplier configuration (1x, 2x, 4x ref)
■ 10 MHz to 166.67 MHz operating range (reference input from
10 MHz to 41.67 MHz)
■ Phase alignment
■ 80 ps typical period jitter
■ Output enable pin
■ 3.3 V operation
■ 5 V tolerant input
■ 8-pin 150-mil small-outline integrated circuit (SOIC) package
■ Commercial temperature range
Functional Description
The CY2303 is a 3 output 3.3 V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
The part allows user to obtain 1x, 2x, and 4x REFIN output
frequencies on respective output pins.
The CY2303 has an on-chip PLL, which locks to an input clock
presented on the REFIN pin. The PLL feedback is internally
connected to the REF output. The input-to-output is guaranteed
to be less than 200 ps, and output-to-output skew is guaranteed
to be less than 200 ps.
Multiple CY2303 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
For a complete list of related documentation, click here.
Logic Block Diagram
FBK
REFIN
x1 REF
PLL
x2 REFx2
x4 REFx4
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07249 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 9, 2016
1 page  
CY2303
Switching Characteristics
Parameter
1/t1
t3
t4
t5
t6
t7
tJ
tLOCK
Name
Test Conditions
Output frequency
18-pF load
12-pF load
Duty cycle [4] = t2 t1
Rise time [4]
Measured at VDD/2
Measured between 0.8 V and 2.0 V
Fall time [4]
Measured between 0.8 V and 2.0 V
Output to output skew on rising All outputs equally loaded
edges [4]
Measured at VDD/2
Delay, REFIN rising edge to REF
rising edge [4]
Measured at VDD/2 from REFIN to
any output
Device to device skew [4]
Measured at VDD/2 on the REF pin
of the device (pin 1)
Period jitter [4]
Measured at FOUT < 133.33 MHz,
loaded outputs, 18-pF load
PLL lock time [4]
Stable power supply, valid clocks
presented on REFIN
Min
10
–
40
–
–
–
–
–
–
–
Typ Max Unit
– 133.33 MHz
– 166.67 MHz
50 60 %
– 1.20 ns
– 1.20 ns
– 200 ps
–
200
ps
– 400 ps
80
175
ps
– 1.0 ms
Note
4. All parameters are specified with loaded outputs.
Document Number: 38-07249 Rev. *J
Page 5 of 14
5 Page 
CY2303
Errata
This section describes the errors, workaround solution and silicon design fixes for Cypress zero delay clock buffers belonging to the
families CY2303. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Table 1. Part Numbers Affected
Part Number
CY2303SXC
CY2303SXCT
Device Variants
All Variants
All Variants
CY2303 Errata Summary
Items
Start up lock time issue [CY2303]
Part Number
All
Fix Status
Silicon fixed. New silicon available from WW 10
of 2013
CY2303 Qualification Status of fixed silicon
Product Status: In production
Qualification report last updated on 11/27/2012
http://www.cypress.com/?rID=72595
1. Start up lock time issue
■ Problem Definition
Output of CY2304 fails to locks within 1 ms upon power up (as per datasheet spec)
■ Parameters Affected
PLL lock time
■ Trigger Condition(s)
Start up
■ Scope of Impact
It can impact the performance of system and its throughput
■ Workaround
Apply reference input (RefClk) before power up (VDD). If RefClk is applied after power up, noise gets coupled on the output and
propagates back to the PLL causing it to take higher time to acquire lock. If reference input is present during power up, noise will
not propagate to the PLL and device will start up normally without problems.
■ Fix Status
This issue is due to design marginality. Two minor design modifications have been made to address this problem.
a. Addition of VCO bias detector block as shown in the following figure keeps comparator power down till VCO bias is present and
thereby eliminating the propagation of noise to feedback.
b. Bias generator enhancement for successful initialization.
Document Number: 38-07249 Rev. *J
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY2303.PDF ] | |
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