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PDF CY2304 Data sheet ( Hoja de datos )
| Número de pieza | CY2304 | |
| Descripción | 3.3V Zero Delay Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2304
3.3V Zero Delay Buffer
Features
• Zero input-output propagation delay, adjustable by
capacitive load on FBK input
• Multiple configurations – see “Available Configura-
tions” table
• Multiple low-skew outputs
— Output-output skew less than 200 ps
— Device-device skew less than 500 ps
• 10-MHz to 133-MHz operating range
• Low jitter, less than 200 ps cycle-cycle
• Space-saving 8-pin 150-mil SOIC package
• 3.3V operation
• Industrial temperature available
Functional Description
The CY2304 is a 3.3V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
The part has an on-chip phase-locked loop (PLL) that locks to
an input clock presented on the REF pin. The PLL feedback is
required to be driven into the FBK pin, and can be obtained
from one of the outputs. The input-to-output skew is
guaranteed to be less than 250 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
The CY2304 has two banks of two outputs each.
The CY2304 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
25 µA of current draw.
Multiple CY2304 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 500 ps.
The CY2304 is available in two different configurations, as
shown in the “Available Configurations” table. The CY2304–1
is the base part, where the output frequencies equal the
reference if there is no counter in the feedback path.
The CY2304–2 allows the user to obtain Ref and 1/2x or 2x
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
feedback pin.
Logic Block Diagram
REF
PLL
FBK
CLKA1
CLKA2
/2 Extra Divider (-2)
CLKB1
Pin Configuration
8-pin SOIC
Top View
REF
CLKA1
CLKA2
GND
1
2
3
4
8 FBK
7 VDD
6 CLKB2
5 CLKB1
CLKB2
Available Configurations
Device
FBK from
CY2304-1
Bank A or B
CY2304-2
Bank A
CY2304-2
Bank B
Bank A Frequency Bank B Frequency
Reference
Reference
Reference
Reference/2
2 × Reference
Reference
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07247 Rev. *C
Revised December 7, 2002
1 page  
CY2304
Switching Characteristics for CY2304SI-X Industrial Temperature Devices (continued)[5]
Parameter
Name
Test Conditions
Min. Typ. Max.
t5
Output-to-Output Skew on All outputs equally loaded
same Bank (–1,–2)[4]
200
Output Bank A to Output Bank All outputs equally loaded
B Skew (–1)
200
Output Bank A to Output Bank All outputs equally loaded
B Skew (–2)
400
t6
Skew, REF Rising Edge to
FBK Rising Edge[4]
Measured at VDD/2
t7
Device-to-Device Skew[4]
Measured at VDD/2 on the FBK pins of
devices
tJ
Cycle-to-Cycle Jitter[4]
Measured at 66.67 MHz, loaded outputs,
(–1) 15-pF load
0 ±250
0 500
180
Measured at 66.67 MHz, loaded outputs,
30-pF load
200
Measured at 133.3 MHz, loaded outputs,
15 pF load
tJ
Cycle-to-Cycle Jitter[4]
Measured at 66.67 MHz, loaded outputs,
(–2) 30-pF load
100
400
tLOCK
PLL Lock Time[4]
Measured at 66.67 MHz, loaded outputs,
15-pF load
Stable power supply, valid clocks
presented on REF and FBK pins
380
1.0
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ms
Electrical Characteristics for CY2304SI-X Industrial Temperature Devices
Parameter
Description
Test Conditions
Min.
VIL
VIH
IIL
IIH
VOL
VOH
IDD (PD mode)
IDD
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage[4]
Output HIGH Voltage[4]
Power-down Supply Current
Supply Current
VIN = 0V
VIN = VDD
IOL = 8 mA (–1, –2)
IOH = –8 mA (–1, –2)
REF = 0 MHz
Unloaded outputs, 100 MHz,
Select inputs at VDD or GND
Unloaded outputs, 66-MHz REF
(–1, –2)
2.0
2.4
Unloaded outputs, 33-MHz REF
(–1, –2)
Switching Waveforms
Max.
0.8
50.0
100.0
0.4
25.0
45.0
35.0
20.0
Unit
V
V
µA
µA
V
V
µA
mA
mA
mA
Duty Cycle Timing
1.4V
t1
t2
1.4V
1.4V
Document #: 38-07247 Rev. *C
Page 5 of 8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CY2304.PDF ] | |
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