PDF CY2300 Data sheet ( Hoja de datos )

Número de pieza	CY2300
Descripción	Phase-Aligned Clock Multiplier
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2300 Phase-Aligned Clock Multiplier Phase-Aligned Clock Multiplier Features ■ 10 MHz to 166.67 MHz output operating range ■ Four-multiplier configuration ■ Single PLL architecture ■ Phase aligned outputs ■ Low jitter, high accuracy outputs ■ Output enable pin ■ 3.3 V operation ■ 5 V tolerant input ■ Internal loop filter ■ 8-pin 150-mil small-outline integrated circuit (SOIC) package ■ Commercial temperature Functional Description The CY2300 is a four output 3.3 V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN output frequencies on respective output pins. The part has an on-chip PLL which locks to an input clock presented on the REFIN pin. The input-to-output skew is guaranteed to be less than 200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2300 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. The CY2300 is available in commercial temperature range. For a complete list of related documentation, click here. Logic Block Diagram FBK REFIN /2 PLL OE Divider Logic 1/2xREF REF REF 2xREF Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-07252 Rev. I • San Jose, CA 95134-1709 • 408-943-2600 Revised December 5, 2016 1 page CY2300 Test Circuits 0.1 F Figure 2. Test Circuit #1 VDD OUTPUTS CLK OUT C LOAD GND Switching Characteristics Parameter 1/t1 t3 t4 t5 t6 t7 tJ tLOCK Description Output frequency Duty cycle[4] = t2 t1 Rise time[4] Fall time[4] Output to output skew on rising edges[4] Delay, REFIN rising edge to output rising edge[4] Device to device skew[4] Period jitter[4] PLL lock time[4] Test Conditions 18 pF load 12 pF load Measured at VDD/2 Measured between 0.8 V and 2.0 V Measured between 0.8 V and 2.0 V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 from REFIN to any output Measured at VDD/2 on the 1/2xREF pin of devices (pin 1) Measured at Fout = 133.33 MHz, loaded outputs, 18 pF load Stable power supply, valid clocks presented on REFIN Min 10 – 40 – – – – – – – Typ Max Unit – 133.33 MHz – 166.67 MHz 50 60 % – 1.20 ns – 1.20 ns – 200 ps – 200 ps – 400 ps – 175 ps – 1.0 ms Note 4. All parameters are specified with equally loaded outputs. Document Number: 38-07252 Rev. I Page 5 of 13 5 Page CY2300 Document Number: 38-07252 Rev. *I Page 11 of 13 11 Page

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