PDF CY28358 Data sheet ( Hoja de datos )

Número de pieza	CY28358
Descripción	200-MHz Differential Clock Buffer/Driver
Fabricantes	Cypress Semiconductor
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No Preview Available ! 58 PRELIMINARY CY28358 200-MHz Differential Clock Buffer/Driver Features Description • Up to 200 MHz operation • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize the outputs to the clock input • Conforms to the DDR1 specification • Spread Aware™ for EMI reduction • 28-pin SSOP package This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential output levels. This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are controlled by the input clock CLKIN and the feed- back clock FBIN. The two line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purpos- es. The PLL in this device uses the input clock CLKIN and the feedback clock FBIN to provide high-performance, low-skew, low–jitter output differential clocks. Block Diagram Pin Configuration SCLK SDATA CLKIN FBIN AVDD 10 Serial Interface Logic PLL CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 FBOUT CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK CLKIN NC AVDD AGND VDD CLKT2 CLKC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 GND 27 CLKC5 26 CLKT5 25 CLKC4 24 CLKT4 23 VDD 22 SDATA 21 NC 20 FBIN 19 FBOUT 18 NC 17 CLKT3 16 CLKC3 15 GND 28 pin SSOP Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07417 Rev. A Revised December 14, 2002 1 page PRELIMINARY Parameter Measurement Information CLKIN 1.25V CY28358 1.25V FBIN 1.25V t(∅)n 1.25V t(∅)n+1 Σt(∅)n = n =N 1 t(∅)n N (N is large number of samples) Figure 1. Static Phase Offset CLKIN 1.25V 1.25V FBIN td(∅) t(∅) td(∅) Figure 2. Dynamic Phase Offset td(∅) t(∅ ) td(∅) CLKT[0:5], FBOUT CLKC[0:5] CLKT[0:5], FBOUT CLKC[0:5] tsk(o) Figure 3. Output Skew Document #: 38-07417 Rev. A Page 5 of 11 5 Page PRELIMINARY CY28358 Document History Page Document Title: CY28358 200-MHz Differential Clock Buffer/Driver Document #: 38-07417 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 118004 09/11/02 INA New Data Sheet A 122925 12/14/02 RBI Add power up requirements to operating condicitons information. Document #: 38-07417 Rev. A Page 11 of 11 11 Page

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