|
|
PDF CY28354-400 Data sheet ( Hoja de datos )
| Número de pieza | CY28354-400 | |
| Descripción | 210-MHz 24-Output Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY28354-400 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
CY28354-400
210-MHz 24-Output Buffer for 4-DDR
DIMMS for VIA Chipsets Support
Features
Functional Description
• Supports VIA PRO 266, KT266 and P4x266
• Dual 1- to 12-output buffer/driver
• Supports up to four DDR DIMMs
• Low-skew outputs (< 75 ps)
• Supports 266-MHz, 333-MHz and 400-MHz DDR SDRAM
• SMBus Read and Write support
• Space-saving 48-pin SSOP package
The CY28354-400 is a 2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs
to support four unbuffered DDR DIMMS. The CY28354-400
can be used in conjunction with CY28326 similar clock synthe-
sizer for the PTT880 and KTT880 chipsets.
The CY28354-400 also includes an SMBus interface which
can enable or disable each output clock. On power-up, all
output clocks are enabled.
Block Diagram
BUF_INA
ADDR_SEL
SDATA
SCLOCK
I2C_CS
SMBus
Decoding
BUFF_INB
FB_OUTA
DDRAT0
DDRAC0
DDRAT1
DDRAC1
DDRAT2
DDRAC2
DDRAT3
DDRAC3
DDRAT4
DDRAC4
DDRAT5
DDRAC5
DDRBT0
DDRBC0
DDRBT1
DDRBC1
DDRBT2
DDRBC2
DDRBT3
DDRBC3
DDRBT4
DDRBC4
DDRBT5
DDRBC5
FB_OUTB
Pin Configuration
VDD2.5
GND
FB_OUTB
BUFF_INB
DDRBT0
DDRBC0
DDRBT1
DDRBC1
GND
VDD2.5
DDRAT0
DDRAC0
DDRAT1
DDRAC1
GND
VDD2.5
FB_OUTA
BUF_INA
DDRAT2
DDRAC2
DDRAT3
DDRAC3
VDD2.5
GND
SSOP
Top View
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
VDD2.5
GND
ADDR_SEL
I2C_CS
DDRBT2
DDRBC2
DDRBT3
DDRBC3
GND
VDD2.5
DDRAT4
DDRAC4
DDRAT5
DDRAC5
GND
VDD2.5
DDRBT4
DDRBC4
DDRBT5
DDRBC5
VDD2.5
GND
SDATA
SCLK
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07615 Rev. *B
Revised June 22, 2004
1 page  
CY28354-400
Absolute Maximum Conditions[1]
Parameter
VDD
Vin
Vout
Ts
Ta
ØJC
ØJA
ESDh
Description
Supply Voltage to Ground Potential
DC Input Voltage (except BUFF_IN)
Output Voltage
Temperature, Storage
Temperature, Operating Ambient
Dissipation, Junction to Case (Mil-Spec 883E Method 1012.1)
Dissipation, Junction to Ambient (JEDEC (JESD 51)
ESD Protection (Human Body Model)
Min.
Max.
–0.5 4.6
–0.3
1.1
–65
VDD+0.3
VDD–0.4
+150
0 85
36.39
77.99
– 2000
Unit
V
V
V
°C
°C
°C/W
°C/W
V
DC Electrical Specifications
Parameter
VDD2.5
COUT
CIN
Supply Voltage
Output Capacitance
Input Capacitance
Description
Min.
2.3
–
–
Typ. Max. Unit
– 2.7 V
6 – pF
5 – pF
AC Electrical Specifications
Parameter
VIL
VIH
IOH
IOL
VOL
VOH
IDD
IDD
IDDPD
VOUT
VOC
INDC
Description
Input LOW Voltage
Input HIGH Voltage
Output HIGH Current
Output LOW Current
Output LOW Voltage[2]
Output HIGH Voltage[2]
Supply Current[2]
Supply Current
Supply Current
Output Voltage Swing
Output Crossing Voltage
Input Clock Duty Cycle
Conditions
For all pins except SMBus
VDD = 2.375V, VOUT = 1V
VDD = 2.375V, VOUT = 1.2V
IOL = 12 mA, VDD = 2.375V
IOH = –12 mA, VDD = 2.375V
Unloaded outputs, 133 MHz
Loaded outputs, 133 MHz
All outputs off
See Test Circuity. See Figure 1
Min.
0.3
1.7
–
–
–
1.7
–
–
–
0.7
VDD/2–0.3
40
Typ.
–
–
–
–
–
–
–
–
–
–
VDD/2
–
Max.
0.7
VDD + 0.3
–12
12
0.5
–
400
500
2
VDD + 0.6
VDD/2+0.3
60
Unit
V
V
mA
mA
V
V
mA
mA
mA
V
V
%
Switching Characteristics[3]
Parameter
Name
Test Conditions
Min. Typ. Max.
– Operating Frequency
60 210
–
Duty Cycle[2, 4] = t2 ÷ t1
Measured differentially at VCROSS
INDC –2% – INDC +2%
t3d DDR Rising Edge Rate[2] Measured single ended at 20% to 80% of VDIF 1.0 2.0 5.0
t4d DDR Falling Edge Rate[2] Measured single ended at 80% to 20% of VDIF 1.0 2.0 5.0
t5
Output to Output Skew for All outputs equally loaded.
DDR[2]
See Figure 1.
– – 75
t6 Input to Output Propagation At output load of 15 pFn
delay
–– 6
Notes:
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3. All parameters specified with loaded outputs.
4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Unit
MHz
%
V/ns
V/ns
ps
ns
Document #: 38-07615 Rev. *B
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY28354-400.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY28354-400 | 210-MHz 24-Output Buffer | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |