PDF CY28352 Data sheet ( Hoja de datos )

Número de pieza	CY28352
Descripción	Differential Clock Buffer/Driver
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY28352 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas
No Preview Available ! CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize output to clock input • Conforms to DDRI specification • Spread Aware™ for electromagnetic interference (EMI) reduction • 28-pin SSOP package This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels. This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are controlled by the input clock CLKIN and the feedback clock FBIN. The two-line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clock CLKIN and the feedback clock FBIN to provide high-performance, low-skew, low–jitter output differential clocks. Block Diagram Pin Configuration SCLK SDATA CLKIN FBIN AVDD 10 Serial Interface Logic PLL CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 FBOUT CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK CLKIN NC AVDD AGND VDD CLKT2 CLKC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 GND 27 CLKC5 26 CLKT5 25 CLKC4 24 CLKT4 23 VDD 22 SDATA 21 NC 20 FBIN 19 FBOUT 18 NC 17 CLKT3 16 CLKC3 15 GND 28 pin SSOP Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07371 Rev. C Revised Sept. 02, 2004 1 page AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C (continued)[7, 9] Parameter Description Condition tPLH LOW-to-HIGH Propagation Delay, CLKIN to CLKT[0:5] tPHL tSKEW tPHASE HIGH-to-LOW Propagation Delay, CLKIN to CLKT[0:5] Any Output to Any Output Skew[11] Phase Error[11] tPHASEJ Phase Error Jitter f > 66 MHz Parameter Measurement Information CLKIN 1.25V CY28352 Min. 1.5 1.5 –150 –50 Typ. Max. 3.5 6 Unit ns 3.5 6 100 150 50 ns ps ps ps 1.25V FBIN CLKIN 1.25V t(∅)n 1.25V t(∅)n+1 Σt(∅)n = n =N 1 t(∅)n (N is large number of samples) Figure 1. Static Phase Offset 1.25V 1.25V FBIN td(∅) CLKT[0:5], FBOUT CLKC[0:5] CLKT[0:5], FBOUT CLKC[0:5] t(∅) td(∅) Figure 2. Dynamic Phase Offset td(∅) t(∅ ) td(∅) tsk(o) Figure 3. Output Skew Document #: 38-07371 Rev. C Page 5 of 8 5 Page

Páginas	Total 8 Páginas
PDF Descargar	[ Datasheet CY28352.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY28351	Differential Clock Buffer/Driver	Cypress Semiconductor
CY28352	Differential Clock Buffer/Driver	Cypress Semiconductor
CY28354-400	210-MHz 24-Output Buffer	Cypress Semiconductor
CY28358	200-MHz Differential Clock Buffer/Driver	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar