PDF CY28351 Data sheet ( Hoja de datos )

Número de pieza	CY28351
Descripción	Differential Clock Buffer/Driver
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the outputs to the clock input • Conforms to the DDRI specification • Spread Aware for electromagnetic interference (EMI) reduction • 48-pin SSOP package This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels. This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT). The clock outputs are individually controlled by the serial inputs SCLK and SDATA. The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for the test purposes. The PLL in this device uses the input clock (CLKIN) and the feedback clock (FBIN) to provide high-performance, low-skew, low-jitter output differential clocks. Block Diagram SCLK SDATA CLKIN FBIN AVDD Serial Interface Logic PLL 10 YT0 YC0 YT1 YC1 YT2 YC2 YT3 YC3 YT4 YC4 YT5 YC5 YT6 YC6 YT7 YC7 YT8 YC8 YT9 YC9 FBOUT Pin Configuration VSS YC0 YT0 VDDQ YT1 YC1 VSS VSS YC2 YT2 VDD SCLK CLKIN NC VDDI AVDD AVSS VSS YC3 YT3 VDDQ YT4 YC4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 VSS 47 YC5 46 YT5 45 VDDQ 44 YT6 43 YC6 42 VSS 41 VSS 40 YC7 39 YT7 38 VDDQ 37 SDATA 36 NC 35 FBIN 34 VDDQ 33 FBOUT 32 NC 31 VSS 30 YC8 29 YT8 28 VDDQ 27 YT9 26 YC9 25 VSS Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07370 Rev. B Revised May 23, 2003 1 page Parameter Measurement Information CLKIN 1.25V CY28351 1.25V FBIN CLKIN 1.25V t(∅)n 1.25V t(∅)n+1 Σt(∅)n = n =N 1 t(∅)n (N is large number of samples) Figure 1. Static Phase Offset 1.25V 1.25V FBIN td(∅) YT[0:9], FBOUT YC[0:9] YT[0:9], FBOUT YC[0:9] t(∅) td(∅) Figure 2. Dynamic Phase Offset td(∅) t(∅ ) td(∅) tsk(o) Figure 3. Output Skew Document #: 38-07370 Rev. B Page 5 of 8 5 Page

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