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PDF SI3460 Data sheet ( Hoja de datos )
| Número de pieza | SI3460 | |
| Descripción | IEEE 802.3af PSE INTERFACE AND DC-DC CONTROLLER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si3460
IEEE 802.3af PSE INTERFACE AND DC-DC CONTROLLER
Features
IEEE 802.3af™ compliant PSE and
dc-dc controller
Autonomous operation requires no
host processor interface
Complete reference design
available, including Si3460 controller,
PSE firmware, and schematic:
Low-cost BOM with compact PCB
footprint
Operates directly from a +12 or
+15 V isolated supply
dc-dc controller generates –48 V
PSE output for SELV compatibility
with telephony interfaces
Supports up to 15.4 W maximum
output power (Class 0)
Applications
Robust 3-point detection
algorithm eliminates false
detection events
IEEE-compliant classification
IEEE-compliant disconnect
Inrush current control
Short-circuit output fault
protection
LED status signal (detect,
power good, output fault)
UNH Interoperability Test Lab test
report available
Extended operating range
(–40 to +85 °C)
11-Pin Quad Flat No-Lead (QFN)
Tiny 3 x 3 mm PCB footprint;
Pb-free, RoHS-compliant
Pin Assignments
Si3460
GATE 1
CTRL1 2
VDD 3
CTRL2 4
250KHZ 5
GND
10 STATUS
9 ISENSE
8 RST
7 VSENSE
6 DETA
11-pin QFN (3x3 mm)
Top View—Pads on bottom of package
IEEE 802.3af endpoints and
midspans
Environment A and B PSEs
Embedded PSEs
Set-top boxes
FTTH media converters
Cable modem and DSL
gateways
Description
The Si3460 is a single-port –48 V power management controller for
IEEE 802.3af-compliant Power Sourcing Equipment (PSE). Designed
to minimize system cost and ease of implementation in embedded
PSE endpoint (switches) or midspan (power injector) applications, the
Si3460 operates directly from a 12 or 15 V input supply and integrates
a digital PWM-based dc-dc converter for generating the –48 V PSE
output supply. The IEEE-required Powered Device (PD) detection
feature uses a robust 3-point algorithm to avoid false detection events.
The Si3460's reference design kit also provides full IEEE-compliant
classification and PD disconnect. Intelligent protection circuitry
includes input undervoltage lockout (UVLO), current limiting, and
output short circuit protection. The Si3460 is designed to operate
completely independently of host processor control. An LED status
signal is provided to indicate the port status, including detect, power
good, and output fault event information for use within the host
system. The Si3460 is pin-programmable to support endpoint and
midspan applications, as well as each of the different classification
power levels specified by the IEEE 802.3af standard. A
comprehensive reference design kit is available (Si3460-EVB),
including a complete schematic and BOM (Bill-of-Materials) for the dc-
dc converter and PSE functions.
Preliminary Rev. 0.4 11/07
Copyright © 2007 by Silicon Laboratories
Si3460
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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Si3460
Table 1. Selected Electrical Specifications (Si3460-EVB)
Parameter
Protection and Current Control
Overload current threshold
Overload current limit
Overload time
Output power at overload
Disconnect current
Efficiency
System efficiency
Symbol
ICUT
ILIM
TLIM
PLIM
IMIN
η
Test Condition
All class levels
Output = 100 Ω across VOUT
Output = 100 Ω across VOUT
Disconnect current
(PIN @ VIN) to (POUT @ VOUT)
Min Typ
15,400/
VOUT
400
50
15.4
5
340
425
60
17
7.5
— 75
Max Unit
400 mA
450 mA
75 ms
—W
10 mA
—%
Preliminary Rev. 0.4
5
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Si3460
5. Si3460-EVB Functional Description
In combination with low-cost external components, the Si3460 controller provides a complete PSE solution for
embedded PoE applications. Included in the Si3460-EVB reference design is a digital PWM controller-based dc-dc
converter that simplifies overall system design by generating the –48 V PSE supply voltage. An isolated 11 to 16 V
input dc supply is all that is needed to supply the Si3460-EVB reference design. Refer to the Si3460-EVB User’s
Guide and schematics for descriptions in the following sections.
5.1. Reset State
At powerup or if reset is held low, the Si3460 is in an inactive state with the PWM turned off (the switcher FET, M1,
is off) and the pass FET, M2, is off.
5.2. Operating Mode Configuration
At powerup, the Si3460 reads the voltage on the STATUS pin, which is set by a resistor divider from VEE to chip
ground. The STATUS pin voltage level configures all of the Si3460's operating modes as summarized in Table 8.
Table 8. Operating Modes
STATUS
Pin Voltage
Operating Mode
Power Level
Supported (W)
Classes Supported
Midspan/
Endpoint
Restart Action on
Fault or Overload
Event Condition
Pin voltage at VEE
(no resistors populated)
15.4
All class levels
Endpoint
Auto restart after 2 s
3.0 V
7.0
Class 1 or 2
Endpoint
Auto restart after 2 s
2.75 V
2.5 V
4.0
Class 1
Endpoint
Auto restart after 2 s
15.4
All class levels
Endpoint
Restart on RST
2.25 V
2.0 V
1.75 V
7.0
Class 1 or 2
Endpoint
Restart on RST
4.0
Class 1
Endpoint
Restart on RST
4.0
Class 1
Midspan
Restart on RST
1.5 V
7.0
Class 1 or 2
Midspan
Restart on RST
1.25 V
1.0 V
15.4 All class levels
4.0 Class 1
Midspan
Midspan
Restart on RST
Auto restart after 2 s
0.5 V
< 0.25 V
(pullup resistor only)
7.0
15.4
Class 1 or 2
All class levels
Midspan
Midspan
Auto restart after 2 s
Auto restart after 2 s
Preliminary Rev. 0.4
11
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet SI3460.PDF ] | |
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