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PDF CY2308 Data sheet ( Hoja de datos )
| Número de pieza | CY2308 | |
| Descripción | 3.3V Zero Delay Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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1CY2308
CY2308
Features
• Zero input-output propagation delay, adjustable by
capacitive load on FBK input
• Multiple configurations, see “Available CY2308
Configurations” table
• Multiple low-skew outputs
— Output-output skew less than 200 ps
— Device-device skew less than 700 ps
— Two banks of four outputs, three-stateable by two
select inputs
• 10-MHz to 133-MHz operating range
• Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4, –5H)
• Space-saving 16-pin 150-mil SOIC package or 16-pin
TSSOP
• 3.3V operation
• Industrial Temperature available
Functional Description
The CY2308 is a 3.3V Zero Delay Buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
The part has an on-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be
driven into the FBK pin, and can be obtained from one of the
outputs. The input-to-output skew is guaranteed to be less
than 350 ps, and output-to-output skew is guaranteed to be
less than 200 ps.
Block Diagram
3.3V Zero Delay Buffer
The CY2308 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the table “Select
Input Decoding.” If all output clocks are not required, Bank B
can be three-stated. The select inputs also allow the input
clock to be directly applied to the output for chip and system
testing purposes.
The CY2308 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
50 µA of current draw. The PLL shuts down in two additional
cases as shown in the “Select Input Decoding” table.
Multiple CY2308 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
The CY2308 is available in five different configurations, as
shown in the “Available CY2308 Configurations” table on page
2. The CY2308–1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The CY2308–1H is the high-drive version of
the –1, and rise and fall times on this device are much faster.
The CY2308–2 allows the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
feedback pin. The CY2308–3 allows the user to obtain 4X and
2X frequencies on the outputs.
The CY2308–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile, and can be used
in a variety of applications.
The CY2308–5H is a high-drive version with REF/2 on both
banks.
Pin Configuration
/2
REF /2
PLL
Extra Divider (–3, –4)
Extra Divider (–5H)
S2 Select Input
S1 Decoding
MUX
/2
Extra Divider (–2, –3)
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
SOIC
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07146 Rev. *C
Revised June 16, 2004
1 page  
CY2308
Switching Characteristics for CY2308SC-XX Commercial Temperature Devices [8]
Parameter
Name
Test Conditions
Min. Typ.
t1
Output Frequency
30-pF load, All devices
t1
Output Frequency
20-pF load, –1H, –5H devices[9]
10
10
t1
Output Frequency
15-pF load, –1, –2, –3, –4 devices
10
Duty Cycle[7] = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66 MHz
(–1, –2, –3, –4, –1H, –5H) 30-pF load
40.0 50.0
Duty Cycle[7] = t2 ÷ t1
Measured at 1.4V, FOUT <50.0 MHz
(–1, –2, –3, –4, –1H, –5H) 15-pF load
45.0 50.0
t3 Rise Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30-pF load
t3 Rise Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15-pF load
t3 Rise Time[7]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30-pF load
t4 Fall Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30-pF load
t4 Fall Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15-pF load
t4 Fall Time[7]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30-pF load
t5 Output to Output Skew on All outputs equally loaded
same Bank
(–1, –2, –3, –4)[7]
Output to Output Skew
(–1H, –5H)
All outputs equally loaded
Output Bank A to Output All outputs equally loaded
Bank B Skew (–1, –4, –5H)
Output Bank A to Output All outputs equally loaded
Bank B Skew (–2, –3)
t6
Delay, REF Rising Edge to
FBK Rising Edge[7]
Measured at VDD/2
0
t7 Device to Device Skew[7] Measured at VDD/2 on the FBK pins of
devices
0
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V on –1H,
1
–5H device using Test Circuit #2
tJ
Cycle to Cycle Jitter[7]
Measured at 66.67 MHz, loaded outputs,
(–1, –1H, –4, –5H)
15-pF load
Measured at 66.67 MHz, loaded outputs,
30-pF load
Measured at 133.3 MHz, loaded outputs,
15-pF load
tJ
Cycle to Cycle Jitter[7]
Measured at 66.67 MHz, loaded outputs
(–2, –3)
30-pF load
tLOCK
PLL Lock Time[7]
Measured at 66.67 MHz, loaded outputs
15-pF load
Stable power supply, valid clocks presented
on REF and FBK pins
Notes:
8. All parameters are specified with loaded outputs.
9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz.
Max.
100
133.3
133.3
60.0
55.0
2.20
1.50
1.50
2.20
1.50
1.25
200
200
200
400
±250
700
200
200
100
400
400
1.0
Unit
MHz
MHz
MHz
%
%
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
V/ns
ps
ps
ps
ps
ps
ms
Document #: 38-07146 Rev. *C
Page 5 of 14
5 Page 
Test Circuits
0.1 µF
0.1 µF
Test Circuit # 1
VDD
OUTPUTS
V DD
GND
GND
CLK OUT
C LOAD
0.1 µF
0.1 µF
CY2308
Test Circuit # 2
V DD
OUTPUTS
V DD
GND
GND
1 KΩ
CLK out
1 KΩ
10 pF
Test Circuit for all parameters except t8
Test Circuit for t8, Output slew rate on –1H, –5 device
Document #: 38-07146 Rev. *C
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY2308.PDF ] | |
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