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PDF PSD813F1A Data sheet ( Hoja de datos )
| Número de pieza | PSD813F1A | |
| Descripción | Flash in-system programmable (ISP) peripherals | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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PSD813F1A
Flash in-system programmable (ISP) peripherals
for 8-bit MCUs, 5 V
NOT FOR NEW DESIGN
FEATURES SUMMARY
■ DUAL BANK FLASH MEMORIES
Figure 1. Packages
– 1 Mbit of Primary Flash Memory (8
Uniform Sectors)
)– 256 Kbit Secondary EEPROM (4 Uniform
t(sSectors)
– Concurrent operation: read from one
ucmemory while erasing and writing the
dother
ro )■ 16 Kbit SRAM
P t(s■ PLD WITH MACROCELLS
te c– Over 3,000 Gates Of PLD: DPLD and
le uCPLD
d– DPLD - User-defined Internal chip-select
so rodecoding
b P– CPLD with 16 Output Macrocells (OMCs)
- O teand 24 Input Macrocells (IMCs)
■ 27 RECONFIGURABLE I/Os
) le– 27 individually configurable I/O port pins
t(s sothat can be used for the following
c bfunctions (16 I/O ports configurable as
uopen-drain outputs):
d - OMCU I/Os
ro )PLD I/Os
P t(sLatched MCU address output; and
te cSpecial function I/Os
le u■ ENHANCED JTAG SERIAL PORT
so rod– Built-in JTAG-compliant serial port allows
full-chip In-System Programmability (ISP)
b P– Efficient manufacturing allows for easy
O teproduct testing and programming
le■ PAGE REGISTER
o– Internal page register that can be used to
s expand the microcontroller address space
b by a factor of 256.
O■ PROGRAMMABLE POWER MANAGEMENT
PQFP52 (M)
PLCC52 (J)
TQFQ64 (U)
■ HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 10,000 Erase/WRITE Cycles of EEPROM
– 1,000 Erase/WRITE Cycles of PLD
– Data Retention: 15-year minimum at 90°C
(for Main Flash, Boot, PLD and
Configuration bits).
■ SINGLE SUPPLY VOLTAGE:
– 5V±10% for 5V
■ STANDBY CURRENT AS LOW AS 50µA
■ Packages are ECOPACK®
October 2008
Rev 5
This is information on a product still in production but not recommended for new designs.
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1 page  
PSD813F1A
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 71
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
)Security, Flash memory and EEPROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
t(sINITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ducAC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Pro t(s)MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
lete ucDC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
so rodPACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
- Ob te PPART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ObsOoblestoelePteroPdruocdt(usc)t(-sO) bsoleREVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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5 Page 
PSD813F1A
Pin Name Pin Type
Description(1)
These pins make up Port A. These port pins are configurable and can have the following
functions:
PA0 29
PA1 28
PA2 27
PA3 25
PA4 24
PA5 23
PA6 22
PA7 21
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
I/O 5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.
6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
)PB0 7
t(sPB1 6
PB2 5
cPB3 4
duPB4 3
roPB5 2
)PB6 52
P t(sPB7 51
soleteroducPC0 20
t(s) - sOoblete PPC1 19
Prodt(usc) - ObPC2 18
ObsOoblestoelePteroducPC3 17
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
These pins make up Port B. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
I/O
2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC0) output.
I/O 3. Input to the PLDs.
4. TMS Input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC1) output.
I/O 3. Input to the PLDs.
4. TCK Input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC2 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
I/O 2. CPLD macrocell (McellBC2) output.
3. Input to the PLDs.
This pin can be configured as a CMOS or Open Drain output.
PC3 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC3) output.
I/O 3. Input to the PLDs.
4. TSTAT output2 for the JTAG Serial Interface.
5. Ready/Busy output for In-System parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
PC4 14
2. CPLD macrocell (McellBC4) output.
I/O 3. Input to the PLDs.
4. TERR output2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PSD813F1A.PDF ] | |
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