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PDF PSD813F1 Data sheet ( Hoja de datos )
| Número de pieza | PSD813F1 | |
| Descripción | Flash In-System Programmable Peripherals | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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PSD813F1
Flash In-System Programmable (ISP)
Peripherals for 8-bit MCUs, 5V
FEATURES SUMMARY
s DUAL BANK FLASH MEMORIES
– 1 Mbit of Primary Flash Memory (8
Uniform Sectors)
– 256 Kbit Secondary EEPROM (4 Uniform
Sectors)
– Concurrent operation: read from one
memory while erasing and writing the
other
s 16 Kbit SRAM (BATTERY-BACKED)
s PLD WITH MACROCELLS
– Over 3,000 Gates Of PLD: DPLD and
CPLD
– DPLD - User-defined Internal chip-select
decoding
– CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
s 27 RECONFIGURABLE I/Os
– 27 individually configurable I/O port pins
that can be used for the following
functions:
MCU I/Os;
PLD I/Os;
Latched MCU address output; and
Special function I/Os.
Note: 16 of the I/O ports may be
configured as open-drain outputs.
s ENHANCED JTAG SERIAL PORT
– Built-in JTAG-compliant serial port allows
full-chip In-System Programmability (ISP)
– Efficient manufacturing allows for easy
product testing and programming
s PAGE REGISTER
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256.
s PROGRAMMABLE POWER MANAGEMENT
Figure 1. Packages
PQFP52 (M)
PLCC52 (J)
TQFQ64 (U)
s HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 10,000 Erase/WRITE Cycles of EEPROM
– 1,000 Erase/WRITE Cycles of PLD
– Data Retention: 15-year minimum at 90°C
(for Main Flash, Boot, PLD and
Configuration bits).
s SINGLE SUPPLY VOLTAGE:
– 5V±10% for 5V
s STANDBY CURRENT AS LOW AS 50µA
August 2004
1/110
1 page  
PSD813F1
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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5 Page 
PSD813F1
Pin Name Pin
PA0 29
PA1 28
PA2 27
PA3 25
PA4 24
PA5 23
PA6 22
PA7 21
PB0 7
PB1 6
PB2 5
PB3 4
PB4 3
PB5 2
PB6 52
PB7 51
PC0 20
PC1 19
PC2 18
PC3 17
PC4 14
Type
Description(1)
These pins make up Port A. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
I/O 5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.
6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
These pins make up Port B. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
I/O
2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC0) output.
I/O 3. Input to the PLDs.
4. TMS Input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC1) output.
I/O 3. Input to the PLDs.
4. TCK Input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC2 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
I/O
2. CPLD macrocell (McellBC2) output.
3. Input to the PLDs.
4. VSTBY – SRAM stand-by voltage input for SRAM battery backup.
This pin can be configured as a CMOS or Open Drain output.
PC3 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC3) output.
I/O 3. Input to the PLDs.
4. TSTAT output2 for the JTAG Serial Interface.
5. Ready/Busy output for In-System parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC4) output.
3. Input to the PLDs.
I/O 4. TERR output2 for the JTAG Interface.
5. Battery-on Indicator output (VBATON). Goes High when power is being drawn from an
external battery.
This pin can be configured as a CMOS or Open Drain output.
11/110
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| PDF Descargar | [ Datasheet PSD813F1.PDF ] | |
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