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PDF AK8181F Data sheet ( Hoja de datos )
| Número de pieza | AK8181F | |
| Descripción | 3.3V LVPECL 1:4 Clock Fanout Buffer | |
| Fabricantes | AKM | |
| Logotipo |  |
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AK8181F
3.3V LVDS 1:4
Preliminary Clock Fanout Buffer
AK8181F
Features
Four differential 3.3V LVDS outputs
Selectable differential PCLK0p/n or LVPECL
clock inputs
PCLK0p/n pair can accept the following
differential input levels; LVDS, LVPECL,
LVHSTL, SSTL, HCSL
PCLK1p/n supports the following input types;
LVPECL, CML, SSTL
Clock output frequency up to 650MHz
Translates any single-ended input signal to
3.3V LVDS levels with resistor bias on
PCLK0n input
Output skew : 30ps (maximum)
Part-to-part skew : 600ps (maximum)
Propagation delay : 2.5ns (maximum)
Operating Temperature Range: -40 to +85℃
Package: 20-pin TSSOP (Pb free)
Pin compatible with ICS8543I
Description
The AK8181F is a member of AKM’s LVDS clock
fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8181F distributes 4 buffered clocks.
AK8181F are derived from AKM’s long-term-
experienced clock device technology, and enable
clock output to perform low skew. The AK8181F is
available in a 20-pin TSSOP package.
Block Diagram
draft-E-02
-1-
Dec-2012
http://www.Datasheet4U.com
1 page  
DC Characteristics (LVCMOS/LVTTL)
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
AK8181F
Parameter
Symbol
Conditions
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VIL
CLK_SEL
Vin=VDD=3.465V
CLK_EN, OE IH Vin=VDD=3.465V
Vin=VSS,
CLK_SEL
VDD=3.465V
IL Vin=VSS,
CLK_EN, OE
VDD=3.465V
MIN
2.0
-0.3
-5
-150
TYP MAX Unit
VDD+0.3
0.8
150
5
V
V
μA
μA
μA
μA
DC Characteristics (Differential)
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol Conditions
MIN TYP MAX Unit
Input High Current
Input Low Current
PCLK0p
PCLK0n
PCLK0p
PCLK0n
Vin=VDD=3.465V
IH Vin=VDD=3.465V
Vin=VSS,
VDD=3.465V
IL Vin=VSS,
VDD=3.465V
-5
-150
150 μA
5 μA
μA
μA
Peak-to-Peak Input Voltage
VPP
0.15
Common Mode Input Voltage (1) (2)
VCMR
VSS+0.5
(1) For single ended applications, the maximum input voltage for PCLK0p and PCLK0n is VDD+0.3V.
(2) Common mode voltage is defined as VIH.
1.3
VDD-0.85
V
V
DC Characteristics (LVPECL)
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol Conditions
MIN TYP
Input High Current
Input Low Current
PCLK1p
PCLK1n
PCLK1p
PCLK1n
Vin=VDD=3.465V
IH Vin=VDD=3.465V
Vin=VSS,
VDD=3.465V
IL Vin=VSS,
VDD=3.465V
-5
-150
Peak-to-Peak Input Voltage
VPP
0.3
Common Mode Input Voltage (1) (2)
VCMR
VSS+1.5
(1) For single ended applications, the maximum input voltage for PCLK1p and PCLK1n is VDD+0.3V.
(2) Common mode voltage is defined as VIH.
MAX
150
5
1.0
VDD
Unit
μA
μA
μA
μA
V
V
draft-E-02
-5-
Dec-2012
5 Page 
Package Information
Mechanical data : 20pin TSSOP
6.50±0.10
0.15±0.05
20 11
AK8181F
1
0.65
0.90±0.05
0.25±0.05
10
0.10 S
S
0°～8°
Marking
20
b AK8181F
XXXXXXX
a
1
11
c
10
a: #1 Pin Index
b: Part number
c: Date code ( 7 digits)
RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
draft-E-02
- 11 -
Dec-2012
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AK8181F.PDF ] | |
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