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PDF AK8181E Data sheet ( Hoja de datos )
| Número de pieza | AK8181E | |
| Descripción | 3.3V LVPECL 1:4 Clock Fanout Buffer | |
| Fabricantes | AKM | |
| Logotipo |  |
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AK8181E
3.3V LVPECL 1:4
Preliminary Clock Fanout Buffer
AK8181E
Features
Four differential 3.3V LVPECL outputs
Selectable crystal or differential clock inputs
Clock output frequency up to 650MHz
Translates any single-ended input signal to
3.3V LVPECL levels with resistor bias on
PCLKn input
Output skew : 10ps (typical)
Part-to-part skew : 150ps (maximum)
Propagation delay : 0.9ns (typical)
Additive phase jitter(RMS):
PCLKp/[email protected] : 0.04ps (typical)
XTAL@50MHz
: 0.14ps (typical)
Operating Temperature Range: -40 to +85℃
Package: 20-pin TSSOP (Pb free)
Pin compatible with ICS8533I-31
Description
The AK8181E is a member of AKM’s LVPECL
clock fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8181E distributes 4 buffered clocks.
AK8181E are derived from AKM’s long-term-
experienced clock device technology, and enable
clock output to perform low skew. The AK8181E is
available in a 20-pin TSSOP package.
Block Diagram
draft-E-01
-1-
Feb-2013
http://www.Datasheet4U.com
1 page  
AK8181E
AC Characteristics
All specifications at VDD= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN TYP MAX Unit
Output Frequency
fOUT
650 MHz
Propagation Delay (1)
Output Skew (2) (3)
Part-to-Part Skew (3) (4)
tPD
tsk(O)
tskPP
0.9 ns
10 ps
150 ps
Buffer Additive Jitter, RMS (5)
PCLKp/n 156.25MHz
(12kHz – 20MHz)
tjit
XTAL 50MHz
(12kHz – 20MHz)
0.04 ps
0.14 ps
Output Rise/Fall Time (5)
tr, tf 20% to 80%
200 600 ps
Output Duty Cycle
DCOUT PCLKp/n
All parameters measured at f ≤ 650MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
(1) Measured from the differential input crossing point to the differential output crossing point.
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions.
50
%
(3) This parameter is defined in accordance with JEDEC Standard 65.
(4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
(5) Design Value
Crystal Characteristics
All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Conditions
MIN TYP MAX
Fundamental
12 50
50
7
1
Unit
MHz
Ω
pF
mW
draft-E-01
-5-
Feb-2013
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet AK8181E.PDF ] | |
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