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PDF CY8C53 Data sheet ( Hoja de datos )
| Número de pieza | CY8C53 | |
| Descripción | Programmable System-on-Chip(PSoC) | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY8C53 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 5 is a true system level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C53 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C53 family can handle dozens of data acquisition channels and analog inputs on
every GPIO pin. The CY8C53 family is also a high-performance configurable digital system with some part numbers including
interfaces such as USB, multi-master I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C53
family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3
microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean
primitives using PSoC® Creator™, a hierarchical schematic design entry tool. The CY8C53 family provides unparalleled opportunities
for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware
updates.
Features
32-bit ARM Cortex-M3 CPU core
DC to 80 MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles,
20-year retention, multiple security features
Up to 64 KB SRAM memory
2-KB electrically erasable programmable read-only memory
(EEPROM) memory, 1 million cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AMBA high-performance bus (AHB) bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5 V input to 1.8 V to
5.0 V output
2 mA at 6 MHz
Low power modes including:
• 2-µA sleep mode with real time clock (RTC) and
low-voltage detect (LVD) interrupt
• 300-nA hibernate mode with RAM retention
Versatile I/O system
28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs[1])
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46x16 segments
CapSense® support from any GPIO[2]
1.2 V to 5.5 V I/O interface voltages, up to 4 domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIOs configurable as open drain high/low,
pull-up/pull-down, High-Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
20 to 24 programmable logic device (PLD) based universal
digital blocks (UDBs)
Full CAN 2.0b 16 RX, 8 TX buffers[1]
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator[1]
www.DaUtpaStohfeoeut4rU16.c-obmit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, and I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
Analog peripherals (1.71 V VDDA 5.5 V)
1.024 V ± 0.1% internal voltage reference across –40 °C to
+85 °C (14 ppm/°C)
Successive approximation register (SAR) analog-to-digital
converter (ADC), 12-bit at 1 Msps
Two 8-bit 8 Msps current digital-to-analog converters (DAC)
(IDACs) or 1 Msps voltage DACs (VDACs)
Four comparators with 95-ns response time
Two uncommitted opamps with 25-mA drive capability
Two configurable multifunction analog blocks. Example
configurations are programmable gain amplifier (PGA),
transimpedance amplifier (TIA), mixer, and sample and hold
CapSense support
Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), single-wire
viewer (SWV), and TRACEPORT interfaces
Cortex-M3 flash patch and breakpoint (FPB) block
Cortex-M3 Embedded Trace Macrocell™ (ETM™)
generates an instruction trace stream.
Cortex-M3 data watchpoint and trace (DWT) generates data
trace information
Cortex-M3 instrumentation trace macrocell (ITM) can be
used for printf-style debugging
DWT, ETM, and ITM blocks communicate with off-chip debug
and trace systems via the SWV or TRACEPORT
Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3- to 74-MHz internal oscillator over full temperature and
voltage range
4- to 33-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 80 MHz
32.768-kHz watch crystal oscillator
Low power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40°C to +85°C degrees industrial temperature
48-pin SSOP, 68-pin QFN, and 100-pin TQFP package
options
Notes
1. This feature on select devices only. See Ordering Information on page 91 for details.
2. GPIOs with opamp outputs are not recommended for use with CapSense
Cypress Semiconductor Corporation
Document Number: 001-55035 Rev. *G
• 198 Champion Court
,• San Jose CA 95134-1709
• 408-943-2600
Revised September 2, 2010
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1 page  
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow VOH
to be set independently of VDDIO when used as outputs. When
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I2C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with Full-Speed USB the USB physical interface is
also provided (USBIO). When not using USB these pins may
also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the “I/O System and Routing” section on page 28 of this
datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 74 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 80 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power internal low speed oscillator (ILO) for the sleep
and watchdog timers. A 32.768-kHz external watch crystal is
also supported for use in real time clock (RTC) applications. The
clocks, together with programmable clock dividers, provide the
flexibility to integrate most timing requirements.
The CY8C53 family supports a wide supply operating range from
1.71 to 5.5 V. This allows operation from regulated supplies such
as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly
from a wide range of battery types. In addition, it provides an
integrated high efficiency synchronous boost converter that can
power the device from supply voltages as low as 0.5 V. This
enables the device to be powered directly from a single battery
or solar cell. In addition, the designer can use the boost converter
to generate other voltages required by the device, such as a
3.3 V supply for LCD glass drive. The boost’s output is available
on the VBOOST pin, allowing other devices in the application to
be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 300-nA hibernate mode with RAM retention and a 2-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 23 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. Using these standard interfaces
enables the designer to debug or program the PSoC with a
variety of hardware solutions from Cypress or third party
vendors. The Cortex-M3 debug and trace modules include FPB,
DWT, ETM, and ITM. These modules have many features to help
solve difficult debug and trace problems. Details of the
programming, test, and debugging interfaces are discussed in
the “Programming, Debug Interfaces, Resources” section on
page 56 of this datasheet.
2. Pinouts
The VDDIO pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-2 and
Figure 2-3. Using the VDDIO pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each VDDIO may sink up to 100 mA total to its
associated I/O pins and opamps. On the 68-pin and 100-pin
devices each set of VDDIO associated pins may sink up to
100 mA. The 48 pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
www.DataSheet4U.com
Document Number: 001-55035 Rev. *G
Page 5 of 102
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PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
The Cortex-M3 CPU subsystem includes these features:
ARM Cortex-M3 CPU
Programmable NVIC, tightly integrated with the CPU core
Full-featured debug and trace modules, tightly integrated with
the CPU core
Up to 128 KB of flash memory, 2 KB of EEPROM, and 32 KB
of SRAM
Cache controller
Peripheral HUB (PHUB)
DMA controller
External memory interface (EMIF)
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
4-GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
The Thumb®-2 instruction set, which offers ARM-level
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
Bit-field control
Hardware multiply and divide
Saturation
If-Then
Wait for events and interrupts
Exclusive access and barrier
Special register access
The Cortex-M3 does not support ARM instructions.
Bit-band support. Atomic bit-level write and read operations.
Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only
be executed at the privileged level. There are also two stack
pointers: Main (MSP) and Process (PSP). These features
support a multitasking operating system running one or more
user-level processes.
Extensive interrupt and system exception support.
4.1.2 Cortex-M3 Operating Modes
The Cortex-M3 operates at either the privileged level or the user
level, and in either the thread mode or the handler mode.
Because the handler mode is only enabled at the privileged level,
there are actually only three states, as shown in Table 4-1.
wwwTa.Dblaeta4S-h1e. eOt4pUe.craotmional Level
Condition
Privileged
User
Running an exception Handler mode Not used
Running main program Thread mode Thread mode
At the user level, access to certain instructions, special registers,
configuration registers, and debugging components is blocked.
Attempts to access them cause a fault exception. At the
privileged level, access to all instructions and registers is
allowed.
The processor runs in the handler mode (always at the privileged
level) when handling an exception, and in the thread mode when
not.
4.1.3 CPU Registers
The Cortex-M3 CPU registers are listed in Table 4-2. Registers
R0-R15 are all 32 bits wide.
Table 4-2. Cortex M3 CPU Registers
Register
R0-R12
Description
General purpose registers R0-R12 have no
special architecturally defined uses. Most
instructions that specify a general purpose
register specify R0-R12.
Low Registers: Registers R0-R7 are acces-
sible by all instructions that specify a general
purpose register.
R13
R14
R15
xPSR
High Registers: Registers R8-R12 are acces-
sible by all 32-bit instructions that specify a
general purpose register; they are not acces-
sible by all 16-bit instructions.
R13 is the stack pointer register. It is a banked
register that switches between two 32-bit stack
pointers: the Main Stack Pointer (MSP) and the
Process Stack Pointer (PSP). The PSP is used
only when the CPU operates at the user level in
thread mode. The MSP is used in all other
privilege levels and modes. Bits[0:1] of the SP
are ignored and considered to be 0, so the SP is
always aligned to a word (4 byte) boundary.
R14 is the Link Register (LR). The LR stores the
return address when a subroutine is called.
R15 is the Program Counter (PC). Bit 0 of the PC
is ignored and considered to be 0, so instructions
are always aligned to a half word (2 byte)
boundary.
The Program status registers are divided into
three status registers, which are accessed either
together or separately:
Application Program Status Register (APSR)
holds program execution status bits such as
zero, carry, negative, in bits[27:31].
Interrupt Program Status Register (IPSR)
holds the current exception number in bits[0:8].
Execution Program Status Register (EPSR)
holds control bits for interrupt continuable and
IF-THEN instructions in bits[10:15] and
[25:26]. Bit 24 is always set to 1 to indicate
Thumb mode. Trying to clear it causes a fault
exception.
Document Number: 001-55035 Rev. *G
Page 11 of 102
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