|
|
PDF CY8C54 Data sheet ( Hoja de datos )
| Número de pieza | CY8C54 | |
| Descripción | Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY8C54 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
PRELIMINARY
PSoC® 5: CY8C54 Family Datasheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 5 is a true system level solution providing MCU, memory, analog, and digital
peripheral functions in a single chip. The CY8C54 family offers a modern method of signal acquisition, signal processing, and control
with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to
ultrasonic signals. The CY8C54 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The
CY8C54 family is also a high performance configurable digital system with some part numbers including interfaces such as USB,
multimaster I2C, and CAN. In addition to communication interfaces, the CY8C54 family has an easy to configure logic array, flexible
routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core. Designers can easily create system
level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design
entry tool. The CY8C54 family provides unparalleled opportunities for analog and digital bill of materials integration while easily
accommodating last minute design changes through simple firmware updates.
Features
32-bit ARM Cortex-M3 CPU core
DC to 67 MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles,
20 year retention, and multiple security features
Up to 64 KB SRAM memory
2 KB EEPROM memory, 1 million cycles, and 20 years
retention
24-channel DMA with multilayer AHB bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low power
Operating voltage range: 2.7 V to 5.5 V
High efficiency boost regulator from 1.8 V input to 5.0 V
output
5 mA at 6 MHz
Low-power modes including:
• 3 µA sleep mode with real time clock and low voltage detect
(LVD) interrupt
• 1 µA hibernate mode with RAM retention
Versatile I/O system
28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO)
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46x16 segments
CapSense® support from any GPIO[2]
1.2 V to 5.5 V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger TTL inputs
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
25 mA sink on SIO
Digital peripherals
20 to 24 programmable PLD based universal digital
blocks (UDB)
Full CAN 2.0b 16 RX, 8 TX buffers[1]
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator
Four 16-bit configurable timer, counter, and PWM blocks
67 MHz, 24-bit fixed point digital filter block (DFB) to
implement FIR and IIR filters
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• LIN bus 2.0
• Quadrature decoder
Analog peripherals (2.7 V ≤ VDDA ≤ 5.5 V)
1.024 V ±1% internal voltage reference across –40 °C to
+85 °C (128 ppm/°C)
Two SAR ADCs, each 12-bit at 1 Msps
Four 8-bit 8 Msps IDACs or 1 Msps VDACs
Four comparators with 95 ns response time
Four uncommitted opamps with 25 mA drive capability
Four configurable multifunction analog blocks. Example
configurations are PGA, TIA. Mixer and Sample and hold
CapSense support
Programming, debug, and trace
Serial wire debug (SWD) and single-wire viewer (SWV)
interfaces
Cortex-M3 flash patch and breakpoint (FPB) block
Cortex-M3 data watchpoint and trace (DWT) generates data
trace information
Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
used for printf-style debugging
DWT and ITM blocks communicate with off-chip debug and
trace systems via the SWV interface
Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3 to 62 MHz internal oscillator over full temperature and
voltage range
4 to 25 MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 67 MHz
32.768 KHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40 °C to +85 °C degrees industrial temperature
68-pin QFN and 100-pin TQFP package options
Notes
1. This feature on select devices only. See Ordering Information on page 97 for details.
2. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
Document Number: 001-66238 Rev. *A
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
Revised June 10, 2011
[+] Feedback
1 page  
PRELIMINARY
PSoC® 5: CY8C54 Family Datasheet
make the SIO function as a general purpose analog comparator.
For devices with FS USB the USB physical interface is also
provided (USBIO). When not using USB these pins may also be
used for limited digital functionality and device programming. All
the features of the PSoC I/Os are covered in detail in the “I/O
System and Routing” section on page 25 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 67 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low power Internal Low Speed Oscillator (ILO) for the sleep
and watchdog timers. A 32.768 KHz external watch crystal is
also supported for use in RTC applications. The clocks, together
with programmable clock dividers, provide the flexibility to
integrate most timing requirements.
The CY8C54 family supports a wide supply operating range from
2.7 to 5.5 V. This allows operation from regulated supplies such
as 3.3 V ± 10% or 5.0 V ± 10%, or directly from a wide range of
battery types. It also provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 1.8 V. The designer can use the boost
converter to generate other voltages required by the device,
such as a 3.3 V supply for LCD glass drive. The boost’s output
is available on the VBOOST pin, allowing other devices in the
application to be powered from the PSoC.
PSoC supports a wide range of low power modes. These include
a 1 µA hibernate mode with RAM retention and a 3 µA sleep
mode with RTC. In the second mode the optional 32.768 KHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 21 of this data sheet.
PSoC uses a a SWD interface for programming, debug, and test.
Using this standard interface enables the designer to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. The Cortex-M3 debug and trace
modules include Flash Patch and Breakpoint (FPB), Data
Watchpoint and Trace (DWT) and Instrumentation Trace
Macrocell (ITM). These modules have many features to help
solve difficult debug and trace problems. Details of the
programming, test, and debugging interfaces are discussed in
the “Programming, Debug Interfaces, Resources” section on
page 53 of this data sheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1 and
Figure 2-2. Using the Vddio pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each Vddio may sink up to 100 mA total to its
associated I/O pins and opamps. On the 68 pin and 100 pin
devices each set of Vddio associated pins may sink up to
100 mA. The 48 pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
Document Number: 001-66238 Rev. *A
Page 5 of 105
[+] Feedback
5 Page 
PRELIMINARY
PSoC® 5: CY8C54 Family Datasheet
Bit-band support. Atomic bit-level write and read operations.
Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only
be executed at the privileged level. There are also two stack
pointers: Main (MSP) and Process (PSP). These features
support a multitasking operating system running one or more
user-level processes.
Extensive interrupt and system exception support.
4.1.2 Cortex-M3 Operating Modes
The Cortex-M3 operates at either the privileged level or the user
level, and in either the thread mode or the handler mode.
Because the handler mode is only enabled at the privileged level,
there are actually only three states, as shown in Table 4-1.
Table 4-1. Operational Level
Condition
Privileged
Running an exception Handler mode
Running main program Thread mode
User
Not used
Thread mode
At the user level, access to certain instructions, special registers,
configuration registers, and debugging components is blocked.
Attempts to access them cause a fault exception. At the
privileged level, access to all instructions and registers is
allowed.
The processor runs in the handler mode (always at the privileged
level) when handling an exception, and in the thread mode when
not.
4.1.3 CPU Registers
The Cortex-M3 CPU registers are listed in Table 4-2. Registers
R0-R15 are all 32 bits wide.
Table 4-2. Cortex M3 CPU Registers
Register
R0-R12
Description
General purpose registers R0-R12 have no
special architecturally defined uses. Most
instructions that specify a general purpose
register specify R0-R12.
Low Registers: Registers R0-R7 are acces-
sible by all instructions that specify a general
purpose register.
High Registers: Registers R8-R12 are acces-
sible by all 32-bit instructions that specify a
general purpose register; they are not acces-
sible by all 16-bit instructions.
R13 R13 is the stack pointer register. It is a banked
register that switches between two 32-bit stack
pointers: the Main Stack Pointer (MSP) and the
Process Stack Pointer (PSP). The PSP is used
only when the CPU operates at the user level in
thread mode. The MSP is used in all other
privilege levels and modes. Bits[0:1] of the SP
are ignored and considered to be 0, so the SP is
always aligned to a word (4 byte) boundary.
R14 R14 is the Link Register (LR). The LR stores the
return address when a subroutine is called.
Table 4-2. Cortex M3 CPU Registers (continued)
Register
R15
xPSR
Description
R15 is the Program Counter (PC). Bit 0 of the PC
is ignored and considered to be 0, so instructions
are always aligned to a half word (2 byte)
boundary.
The Program status registers are divided into
three status registers, which are accessed either
together or separately:
Application Program Status Register (APSR)
holds program execution status bits such as
zero, carry, negative, in bits[27:31].
Interrupt Program Status Register (IPSR)
holds the current exception number in bits[0:8].
Execution Program Status Register (EPSR)
holds control bits for interrupt continuable and
IF-THEN instructions in bits[10:15] and
[25:26]. Bit 24 is always set to 1 to indicate
Thumb mode. Trying to clear it causes a fault
exception.
PRIMASK
A 1-bit interrupt mask register. When set, it
allows only the nonmaskable interrupt (NMI) and
hard fault exception. All other exceptions and
interrupts are masked.
FAULTMASK A 1-bit interrupt mask register. When set, it
allows only the NMI. All other exceptions and
interrupts are masked.
BASEPRI
A register of up to nine bits that define the
masking priority level. When set, it disables all
interrupts of the same or higher priority value. If
set to 0 then the masking function is disabled.
CONTROL A 2-bit register for controlling the operating
mode.
Bit 0: 0 = privileged level in thread mode, 1 = user
level in thread mode.
Bit 1: 0 = default stack (MSP) is used, 1 =
alternate stack is used. If in thread mode or user
level then the alternate stack is the PSP. There
is no alternate stack for handler mode; the bit
must be 0 while in handler mode.
4.2 Cache Controller
The CY8C54 family has 1 KB instruction cache between the CPU
and the flash memory. This improves instruction execution rate
and reduces system power consumption by requiring less
frequent flash access.
4.3 DMA and PHUB
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
Document Number: 001-66238 Rev. *A
Page 11 of 105
[+] Feedback
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C54.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY8C52 | Programmable System-on-Chip | Cypress Semiconductor |
| CY8C53 | Programmable System-on-Chip(PSoC) | Cypress Semiconductor |
| CY8C54 | Programmable System-on-Chip | Cypress Semiconductor |
| CY8C56LP | Programmable System-on-Chip | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |