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PDF CY8C52 Data sheet ( Hoja de datos )
| Número de pieza | CY8C52 | |
| Descripción | Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
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Hay una vista previa y un enlace de descarga de CY8C52 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRELIMINARY
PSoC® 5: CY8C52 Family Datasheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 5 is a true system-level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on
every GPIO pin. The CY8C52 family is also a high-performance configurable digital system with some part numbers including inter-
faces such as USB, multimaster I2C, and controller area network (CAN), a communications protocol. In addition to communication
interfaces, the CY8C52 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM®
Cortex™-M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and
boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52 family provides unparalleled
opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple
firmware updates.
Features
32-bit ARM Cortex-M3 CPU core
DC to 40 MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles,
20-year retention and multiple security features
Up to 64 KB SRAM memory
2-KB electrically erasable programmable read-only memory
(EEPROM) memory, 1 million cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AMBA high-performance bus (AHB) bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low power
Operating voltage range: 2.7 V to 5.5 V
High efficiency boost regulator from 1.8-V input to 5.0-V
output
5 mA at 6 MHz
Low power modes including:
• 3-µA sleep mode with real time clock (RTC) and
low-voltage detect (LVD) interrupt
• 1-µA hibernate mode with RAM retention
Versatile I/O system
28 to 72 I/Os (62 GPIOs, eight SIOs, two USBIOs[1])
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense® support from any GPIO[2]
1.2 V to 5.5 V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt trigger transistor-transistor logic (TTL) inputs
All GPIOs configurable as open drain high/low, pull up/down,
High-Z, or strong output
25 mA sink on SIO
Digital peripherals
20 to 24 programmable logic device (PLD) based universal
digital blocks (UDBs)
Full CAN 2.0b 16 RX, 8 TX buffers[1]
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator[1]
Four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, and I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
Analog peripherals (2.7 V ≤ VDDA ≤ 5.5 V)
1.024 V ±1% internal voltage reference across –40 °C to
+85 °C (128 ppm/°C)
Successive approximation register (SAR) analog-to-digital
converter (ADC), 12-bit at 1 Msps
One 8-bit, 8-Msps current DAC (IDAC) or 1-Msps voltage
DAC (VDAC)
Two comparators with 95-ns response time
CapSense support
Programming, debug, and trace
Serial wire debug (SWD) and single-wire viewer (SWV)
interfaces
Cortex-M3 flash patch and breakpoint (FPB) block
Cortex-M3 data watchpoint and trace (DWT) generates data
trace information
Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
used for printf-style debugging
DWT and ITM blocks communicate with off-chip debug and
trace systems via the SWV interface
Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3 to 24 MHz internal oscillator over full temperature and
voltage range
4 to 25 MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 40 MHz
32.768 KHz watch crystal oscillator
Low power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40 °C to +85 °C degrees industrial temperature
68-pin QFN and 100-pin TQFP package options
Notes
1. This feature on select devices only. See Ordering Information on page 88 for details.
2. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
Document Number: 001-66236 Rev. *A
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
Revised June 10, 2011
1 page  
PRELIMINARY
PSoC® 5: CY8C52 Family Datasheet
PSoC uses a SWD interface for programming, debug, and test.
Using this standard interface enables the designer to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. The Cortex-M3 debug and trace
modules include FPB, DWT, and ITM. These modules have
many features to help solve difficult debug and trace problems.
Details of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 49 of this data sheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1 and
Figure 2-2. Using the Vddio pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each Vddio may sink up to 100 mA total to its
associated I/O pins. On the 68-pin and 100-pin devices each set
of Vddio associated pins may sink up to 100 mA. The 48 pin
device may sink up to 100 mA total for all Vddio0 plus Vddio2
associated I/O pins and 100 mA total for all Vddio1 plus Vddio3
associated I/O pins.
Figure 2-1. 68-pin QFN Part Pinout[3]
(GPIO) P2[6]
(GPIO) P2[7]
(SIO) P12[4]
(SIO) P12[5]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
(SWDIO, GPIO) P1[0]
(SWDCK, GPIO) P1[1]
(GPIO) P1[2]
(SWV, GPIO) P1[3]
(GPIO) P1[4]
(GPIO) P1[5]
Vddio1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Lines show Vddio
to I/O supply
association
QFN
(Top View)
51 P0[3] (GPIO, OpAmp0-/Extref0)
50 P0[2] (GPIO, OpAmp0+)
49 P0[1] (GPIO, OpAmp0out)
48 P0[0] (GPIO, OpAmp2out)
47 P12[3] (SIO)
46 P12[2] (SIO)
45 Vssd
44 Vdda
43 Vssa
42 Vcca
41 P15[3] (GPIO, kHz XTAL: Xi)
40 P15[2] (GPIO, kHz XTAL: Xo)
39 P12[1] (SIO)
38 P12[0] (SIO)
37 P3[7] (GPIO, OpAmp3out)
36 P3[6] (GPIO, OpAmp1out)
35 Vddio3
Notes
3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-66236 Rev. *A
Page 5 of 95
5 Page 
PRELIMINARY
PSoC® 5: CY8C52 Family Datasheet
Table 4-2. Cortex M3 CPU Registers (continued)
Register
CONTROL
Description
A 2-bit register for controlling the operating
mode.
Bit 0: 0 = privileged level in thread mode,
1 = user level in thread mode.
Bit 1: 0 = default stack (MSP) is used,
1 = alternate stack is used. If in thread mode or
user level then the alternate stack is the PSP.
There is no alternate stack for handler mode; the
bit must be 0 while in handler mode.
4.2 Cache Controller
The CY8C52 family has a 1 KB cache between the CPU and the
flash memory. This improves instruction execution rate and
reduces system power consumption by requiring less frequent
flash access.
4.3 DMA and PHUB
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.3.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight multi-layer AHB bus parallel access paths (spokes) for
peripheral access
Simultaneous CPU and DMA access to peripherals located on
different spokes
Simultaneous DMA source and destination burst transactions
on different spokes
Supports 8-, 16-, 24-, and 32-bit addressing and data
Table 4-3. PHUB Spokes and Peripherals
PHUB Spokes
Peripherals
0 SRAM
1 IOs, PICU
2 PHUB local configuration, Power manager,
Clocks, IC, EEPROM, Flash programming
interface
3 Analog interface and trim, Decimator
4 USB, CAN, I2C, Timers, Counters, and PWMs
5 Reserved
6 UDBs group 1
7 UDBs group 2
4.3.2 DMA Features
24 DMA channels
Each channel has one or more transaction descriptors (TDs)
to configure channel behavior. Up to 127 total TDs can be
defined
TDs can be dynamically updated
Eight levels of priority per channel
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
Supports transaction size of infinite or 1 to 64 k bytes
Large transactions may be broken into smaller bursts of 1 to
127 bytes
TDs may be nested and/or chained for complex transactions
Document Number: 001-66236 Rev. *A
Page 11 of 95
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C52.PDF ] | |
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