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PDF PI74ALVCH162268 Data sheet ( Hoja de datos )
| Número de pieza | PI74ALVCH162268 | |
| Descripción | 12-Bit To 24-Bit Registered Bus Exchanger | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PI74ALVCH162268 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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12-Bit To 24-Bit Registered Bus Exchanger
with 3-State Outputs
Product Features
• PI74ALVCH162268 is designed for low voltage operation
VCC = 2.3V to 3.6V
• Hysteresis on all inputs
www.DataS•heTety4pUi.ccaolmVOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• B-port outputs have equivalent 26Ω series resistors,
no external resistors are required.
• Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A56)
– 56-pin 300 mil wide plastic SSOP (V56)
Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
This 12-bit to 24-bit registered bus exchanger is designed for 2.3V
to 3.6V Vcc operation.
The PI74ALVCH162268 is used for applications in which data
must be transferred from a narrow high-speed bus to a wide, lower
frequency bus.
The device provides synchronous data exchange between the two
ports. Data is stored in the internal registers on the low-to-high
transition of the clock (CLK) input when the appropriate clock
enable (CLKEN) inputs are low. The select (SEL) line is
synchronous with CLK and selects 1B or 2B input data for the A
outputs.
For data transfer in the A-to-B direction, a two stage pipeline is
provided in the A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of these inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the
B-port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered so bus direction
changes are synchronous with CLK.
The B outputs, which are designed to sink up to 12mA, include
equivalent 26Ω resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to VCC through a pullup resistor, the minimum value
of the resistor is determined by the current-sinking capability of
the driver. Because OE is being routed through a register, the
active state of the outputs cannot be determined prior to the arrival
of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1 PS8352 11/04/98
1 page  
PI74ALVCH162268
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Timing Requirements over Operating Range
Parameters
Description
VCC= 2.5 V ± 0.2 V
Min.
Max.
VCC= 2.7 V
Min. Max.
fCLOCK
tW
Clock frequency
Pulse duration,
CLK high or Low
0 120 0 125
3.3 3.3
A data before CLK↑
4.5
4
B data before CLK↑
0.8
1.2
www.DataSheet4tUSU.com Setup time
SEL before CLK↑
CLKENA1 or CLKENA2
before CLK↑
1.4
3.6
1.6
3.4
CLKENB1 or CLKENB2
before CLK↑
3.2
3
OE before CLK↑
4.2
3.9
A data after CLK↑
0
0
B data after CLK↑
1.3
1.2
SEL after CLK↑
1
1
tH Hold time
CLKENA1 or CLKENA2
after CLK↑
0.1
0.1
CLKENB1 or CLKENB2
after CLK↑
0.1
0
OE after CLK↑
0
0
∆t/∆v(1)
Input Transition
Rise or Fall
0 10 0 10
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
VCC= 3.3 V ± 0.3 V
Min.
Max.
0 150
3.3
3.4
1
1.3
2.8
2.5
3.2
0.2
1.3
1
0.4
0.5
0.2
0 10
Units
Mhz
ns
ns
ns
ns/V
Switching Characteristics over Operating Range(1)
Parameters
From
(INPUT)
To
(OUTPUT)
VCC = 2.5V ± 0.2V
Min.(2)
Max.
VCC = 2.7V
Min.(2) Max.
VCC = 3.3V ± 0.3V
Min.(2)
Max.(2)
fMAX
120 125 150
tPD
B 1.6 6.1
5.9 1.8
5.4
tPD
A (1B) 1.6 5.8
5.4 1.7
4.8
tPD
B (2B) 1.6 5.8
5.3 1.8
4.8
tPD
A (SEL)
2.5
7.3
CLK
tEN B 2.7 7.2
6.5 2.4
6.8 2.6
5.8
6.1
tDIS
B 2.8 7.2
6.1 2.5
5.9
tEN
A 2 6.2
5.6 1.8
5.1
tDIS
A 2 6.5
5.4 2.1
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
5
Units
MHz
ns
5 PS8352 11/04/98
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PI74ALVCH162268.PDF ] | |
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