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PDF PI74ALVCH1622601 Data sheet ( Hoja de datos )
| Número de pieza | PI74ALVCH1622601 | |
| Descripción | 18-Bit Universal Bus Transceiver With 3-State Outputs | |
| Fabricantes | ETC | |
| Logotipo |  |
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PI74ALVCH1622601
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18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Features
• PI74ALVCH1622601is designed for low voltage operation
• VCC=2.3Vto3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Inputs/Outputs have equivalent 26Ω series resistors,
no external resistors are required.
• Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH1622601 uses D-type latches and D-type flip-
flops with 3-state outputs to allow data flow in transparent, latched,
and clocked modes.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latched Enable (LEAB and LEBA), and Clock
(CLKAB and CLKBA) inputs. The clock can be controlled by the
Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B
data flow, the device operates in the transparent mode when LEAB
is HIGH. When LEAB is LOW, the A data is latched if CLKAB is
held at a high or low logic level. If LEAB is low, the A-bus is stored
in the latch/flip-flop on the low-to-high transition of CLKAB.
When OEAB is low, the outputs are active. When OEAB is HIGH,
the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, CLKBA, and CLKENBA.
To reduce overshoot and undershoot, the inputs/outputs include
26Ω series resistors.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH1622601 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
1 PS8115B 02/03/98
1 page  
PI74ALVCH1622601
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Timing Requirements over Operating Range
Parameters
Description
fCLOCK
tW Pulse
Duration
Clock frequency
LE high
CLK high or low
VCC= 2.5 V ± 0.2 V
Min. Max.
0 140
3.3
3.3
VCC= 2.7 V
VCC= 3.3 V ± 0.3 V
Units
Min. Max. Min. Max.
0 150 0 150 MHz
3.3 3.3
3.3 3.3
Data before CLK high
tSU Setup Data before LE low, CLK high
time Data before LE low, CLK low
CLKEN before CLK high
2.3
2.0
1.3
2.0
2.4 2.1
1.6 1.6
1.2 1.1
ns
2.0 1.7
Data after CLK high
0.7
0.7 0.8
tH Hold
time
Data after LE low, CLK high
Data after LE low, CLK low
1.3
1.7
1.6
2.0
Dt/Dv(1)
CLKEN after CLK high
Input Transition Rise or Fall
0.3 0.5
0 10 0
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
Switching Characteristics over Operating Range(1)
10
1.4
1.7
0.6
0
10 ns/V
Parameters
From
(INPUT)
To
(OUTPUT)
VCC= 2.5 V ± 0.2 V
Min.(2)
Max.
VCC= 2.7 V
Min.(2) Max.
VCC= U3.3 V ± 0.3 V
Min.(2)
Max.
Units
fMAX
140
tPD A B 1.8 5.4
tPD B A 1.8 5.4
tPD
LEAB
B
1.5 6.1
tPD
LEBA
A
1.5 6.1
tPD
CLKAB
B
2 6.7
tPD
CLKBA
A
1.2 6.7
tEN
OEAB
B
1.7 6.6
tDIS
OEAB
B
2.5 5.9
tEN
OEBA
A
1.7 6.6
tDIS
OEBA
A
2.5 5.9
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
150
5.2
5.2
5.9
5.9
6.3
6.3
6.7
5.3
6.7
5.3
150
1.6
1.6
1.5
1.5
1.6
1.6
1.6
1.8
1.6
1.8
MHz
4.5
4.5
5.1
5.1
5.5
ns
5.5
5.7
4.8
5.7
4.8
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5 PS8115B 02/03/98
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PI74ALVCH1622601.PDF ] | |
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