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PDF CY28341 Data sheet ( Hoja de datos )
| Número de pieza | CY28341 | |
| Descripción | Universal Single-Chip Clock Solution | |
| Fabricantes | SpectraLinear | |
| Logotipo |  |
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CY28341
Universal Single-Chip Clock Solution for VIA P4M266/KM266
DDR Systems
Features
• Supports VIA¥ P4M266/KM266 chipsets
• Supports Pentium® 4, Athlon™ processors
• Supports two DDR DIMMS
www.DataShe•etS4Uup.cpoomrts three SDRAMS DIMMS at 100 MHz
• Provides:
— Two different programmable CPU clock pairs
— Six differential SDRAM DDR pairs
— Three low-skew/low-jitter AGP clocks
— Seven low-skew/low-jitter PCI clocks
— One 48M output for USB
— One programmable 24M or 48M for SIO
• Dial-a-Frequency™ and Dial-a-dB¥ features
• Spread Spectrum for best electromagnetic interference
(EMI) reduction
• Watchdog feature for systems recovery
• SMBus-compatible for programmability
• 56-pin SSOP and TSSOP packages
Table 1. Frequency Selection Table
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1100
1111
CPU
66.80
100.00
120.00
133.33
72.00
105.00
160.00
140.00
77.00
110.00
180.00
150.00
90.00
100.00
200.00
133.33
AGP
66.80
66.80
60.00
66.67
72.00
70.00
64.00
70.00
77.00
73.33
60.00
60.00
60.00
66.67
66.67
66.67
PCI
33.40
33.40
30.00
33.33
36.00
35.00
32.00
35.00
38.50
36.67
30.00
30.00
30.00
33.33
33.33
33.33
Block Diagram
Pin Configuration[1]
XIN
XOUT
PD#
XTAL
FS0
PLL1
FS2
FS3 FS1
VDDR
REF0
SELP4_K7#
SDATA
SCLK
SMBus
PLL2
WDEN
/2
WD
Buf_IN
SELSDR_DDR
S2D
CONVERT
REF(0:1)
VDDI
CPUCS_T/C
VDDC
CPU(0:1)/CPU0D_T/C
VDDPCI
PCI(3:6)
PCI_F
MULTSEL
PCI2
PCI1
VDDAGP
AGP(0:2)
VDD48M
48M
24_48M
SRESET#
VDDD
FBOUT
DDRT(0:5)/SDRAM(0,2,4,6,8,10)
DDRC(0:5)/SDRAM(1,3,5,7,9,11)
*FS0/REF0
VSSR
XIN
XOUT
VDDAGP
AGP0
*SELP4_K7/AGP1
AGP2
VSSAGP
**FS1/PCI_F
**SELSDR_DDR/PCI1
*MULTSEL/PCI2
VSSPCI
PCI3
PCI4
VDDPCI
PCI5
PCI6
VSS48M
**FS3/48M
**FS2/24_48M
VDD48M
VDD
VSS
IREF
*PD#/SRESET#
SCLK
SDATA
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
1 56 VTTPWRGD#/REF1
2 55 VDDR
3 54 VSSC
4 53 CPUT/CPUOD_T
5 52 CPUC/CPUOD_C
6 51 VDDC
7 50 VDDI
8 49 CPUCS_C
9 48 CPUCS_T
10 47 VSSI
11 46 FBOUT
12 45 BUF_IN
13 44 DDRT0/SDRAM0
14 43 DDRC0/SDRAM1
15 42 DDRT1/SDRAM2
16 41 DDRC1/SDRAM3
17 40 VDDD
18 39 VSSD
19 38 DDRT2/SDRAM4
20 37 DDRC2/SDRAM5
21 36 DDRT3/SDRAM6
22 35 DDRC3/SDRAM7
23 34 VDDD
24 33 VSSD
25 32 DDRT4/SDRAM8
26 31 DDRC4/SDRAM9
27 30 DDRT5/SDRAM10
28 29 DDRC5/SDRAM11
56 pin SSOP
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 19
www.SpectraLinear.com
1 page  
CY28341
Table 4. Byte Read and Byte Write Protocol
Bit
1
2:8
9
10
11:18
www.DataSheet4U.com
19
20:27
28
29
Byte Write Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits “1xxxxxxx” stands for
byte operationbit[6:0] of the command code
represents the offset of the byte to be accessed
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Stop
Serial Control Registers
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits “1xxxxxxx” stands for
byte operationbit[6:0] of the command code
represents the offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte 0: Frequency Select Register
Bit
@Pup
Pin#
70
6
H/W Setting
21
5
H/W Setting
10
4 H/W Setting 1
30
2
H/W Setting
11
1
H/W Setting
20
0 H/W Setting 7
Name
Description
Reserved Reserved
FS2 For Selecting Frequencies see Table 1.
FS1 For Selecting Frequencies see Table 1.
FS0 For Selecting Frequencies see Table 1.
If this bit is programmed to “1,” it enables Write to bits (6:4,1) for
selecting the frequency via software (SMBus). If this bit is
programmed to a “0,” it enables only Read of bits (6:4,1), which
reflects the hardware setting of FS(0:3).
SELSDR_DDR Only for reading the hardware setting of the SDRAM interface
mode, status of SELSDR_DDR# strapping.
FS3 For Selecting frequencies see Table 1
SELP4_K7 Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.
Byte 1: CPU Clocks Register
Bit @Pup Pin#
70
Name
MODE
Description
0 = Down Spread. 1 = Center Spread. See Table 9.
61
SSCG
1 = Enable (default). 0 = Disable
51
SST1
Select spread bandwidth. See Table 9.
41
SST0
Select spread bandwidth. See Table 9.
3 1 48,49 CPUCS_T, CPUCS_C 1 = output enabled (running). 0 = output disabled asynchronously in a LOW
state.
2 1 53,52 CPUT/CPUOD_T 1 = output enabled (running). 0 = output disable.
CPUC/CPUOD_C
Rev 1.0, November 20, 2006
Page 5 of 19
5 Page 
CY28341
AC Parameters (continued)
Parameter
Description
100 MHz
Min. Max.
133MHz
Min. Max
200 MHz
Min.
Max Unit Notes[4]
TSKEW CPUCS_T/C to CPUT/C Clock
0
200
0 150 0 200 ps 11,15,21,22
Skew
TCCJ
CPUT/C Cycle to Cycle Jitter
–150
+150
–150 +150 –200 +200 ps 11,15,21,22
Vcross Crossing Point Voltage at 0.7V 280 430 280 430 280 430 mV 22
Swing
P4 Mode CPU at 1.0V
TDC
CPUT/C Duty Cycle
www.DataSheet4U.com
TPeriod CPUT/C Period
45 55 45 55 45 55 % 11,14,21
9.85
10.2
7.35 7.65 4.85
5.1 nS 11,14,21
Differential CPUT/C Rise and Fall Times 175 467 175 467 175 467 ps 13,15,25
Tr/Tf
TSKEW CPUCS_T/C to CPUT/C Clock
0
200
0 150 0 200 0 11,15,21
Skew
TCCJ
CPUT/C Cycle to Cycle Jitter
–150
+150
–150 +150 –200 +200 ps 11,15,21
Vcross Crossing Point Voltage at 1V 510 760 510 760 510 760 mV 26
Swing
SE- Absolute Single-ended Rise/Fall
DeltaSlew Waveform Symmetry
325
325
325 ps
24,31
K7 Mode
TDC
CPUOD_T/C Duty Cycle
45 55 45 55 45 55 % 11,14
TPeriod CPUOD_T/C Period
9.98 10.5
7.5 8.0
5
5.5 ns
11,14
TLOW
CPUOD_T/C LOW Time
2.8
1.67 2.8 ns 11,14
Tf CPUOD_T/C Fall Time
0.4
1.6
0.4
1.6
0.4
1.6 ns
11,13
TSKEW CPUCS_T/C to CPUT/C Clock
0
200
0 150 0 200 0 11,15,21
Skew
TCCJ
CPUOD_T/C Cycle to Cycle
Jitter
–150
+150
–150 +150 –200 +200 ps
11,14
VD Differential Voltage AC
0.4 Vp+.6V 0.4 Vp+.6V 0.4 Vp+.6V V
20
VX
Differential Crossover Voltage
500
1100
500 1100 500 1100 mV
19
CHIPSET CLOCK
TDC
CPUCS_T/C Duty Cycle
45 55 45 55 45 55 % 7,11,14
TPeriod CPUCS_T/C Period
10.0 10.5
15 15.5 10.0 10.5 ns 7,11,14
Tr / Tf
CPUCS_T/C Rise and Fall Times 0.4
1.6
0.4 1.6 0.4 1.6 ns 7,11,13
VD Differential Voltage AC
0.4 Vp+.6V 0.4 Vp+.6V 0.4 Vp+.6V V
27
VX
Differential Crossover Voltage 0.5*VDDI 0.5*VDDI + 0.5*VDDI 0.5*VDDI 0.5*VDDI 0.5*VDDI V
21
– 0.2 0.2 – 0.2 + 0.2 – 0.2 + 0.2
AGP
TDC
AGP(0:2) Duty Cycle
45 55 45 55 45 55 % 7,11,14
TPeriod AGP(0:2) Period
15 16 15 16 15 16 ns 7,11,14
THIGH AGP(0:2) HIGH Time
5.25
5.25 5.25 ns 11,16
TLOW
AGP(0:2) LOW Time
5.05
5.05 5.05 ns 11,17
Tr / Tf
AGP(0:2) Rise and Fall Times
0.4
1.6
0.4
1.6
0.4
1.6 ns
11,13
TSKEW Any AGP to Any AGP clock Skew
250
250
250 ps
11,15
TCCJ
AGP(0:2) Cycle to Cycle Jitter
500
500 500 ps 11,14,15
PCI
TDC
PCI(_F,1:6) Duty Cycle
45 55 45 55 45 55 % 7,11,14
TPeriod PCI(_F,1:6) Period
30.0
30.0 30.0 ns 7,11,14
Rev 1.0, November 20, 2006
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY28341.PDF ] | |
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