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PDF CY28342 Data sheet ( Hoja de datos )
| Número de pieza | CY28342 | |
| Descripción | High-performance SiS645/650 Pentium 4 Clock Synthesizer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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42
CY28342
High-performance SiS645/650 Pentium 4 Clock Synthesizer
Features
• Supports Pentium 4-type CPUs
• 3.3V power supply
• Eight copies of PCI clocks
• One 4-MHz USB clock
• Two copies of ZCLK clocks
• One 48-MHz/24-MHz programmable SIO clock
• Two differential CPU clock pairs
• SMBus support with read-back capabilities
• Spread Spectrum EMI reduction
• Dial-a-Frequency® features
• Dial-a-Ratio™ features
• Dial-a-dB® features
• 48-pin SSOP and TSSOP packages
• Watchdog Function
Block Diagram
Pin Configuration[1]
XIN
XOUT
CPU_STP#
IREF
FS(0:4)
MULT0
VTTPWRGD
PCI_STP#
PLL1
Power
on
Latch
PLL2
PD#
SDATA
SCLK
WD
Logic
I2C
Logic
/2
REF(0:2)
CPU(0:1)T
CPU(0:1)C
SDCLK
AGP(0:1)
ZCLK(0:1)
PCI(0:5)
PCI_F(0:1)
48M
48M_24M#
SRESET#
VDDR
**FS0/REF0
**FS1/REF1
**FS2/REF2
VSSR
XIN
XOUT
VSSZ
ZCLK0
ZCLK1
VDDZ
*SRESET#/PCI_STP#
VDDP
**FS3/PCI_F0
**FS4/PCI_F1
PCI0
PCI1
VSSP
VDDP
PCI2
PCI3
PCI4
PCI5
VSSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDSD
47 SDCLK
46 VSSSD
45 CPU_STP#*
44 CPU1T
43 CPU1C
42 VDDC
41 VSSC
40 CPU0T
39 CPU0C
38 IREF
37 VSSA
36 VDDA
35 SCLK
34 SDATA
33 PD#/VTTPWRGD*
32 VSSAGP
31 AGP0
30 AGP1
29 VDDAGP
28 VDD48M
27 48M
26 24_48M/MULT0*
25 VSS48M
48 Pin SSOP andf TSSOP
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07349 Rev. *A
Revised July 29, 2002
1 page  
CY28342
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block Read or block Write operation
1 = Byte Read or byte Write operation
Byte offset for byte Read or byte Write operations. For block Read or block Write operations, these bits
should be “0000000”
Table 3. Block Read and Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
Block Write Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command code – 8-bit “00000000” stands for
block operation
Acknowledge from slave
Byte count –8 bits
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte N/slave acknowledge...
Data byte N – 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Block Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command code – 8-bit “00000000” stands for
block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/acknowledge
Data byte N from slave – 8 bits
Not acknowledge
Stop
Table 4. Byte Read and Byte Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29
Byte Write Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bit “1xxxxxxx” stands for
byte operation bit[6:0] of the command code
represents the offset of the byte to be accessed
Acknowledge from slave
Byte count – 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8-bit “1xxxxxxx” stands for
byte operation bit[6:0] of the command code
represents the offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Document #: 38-07349 Rev. *A
Page 5 of 22
5 Page 
CY28342
System Self-recovery Clock Management
This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang up due to the
frequency change.
When the system sends an SMBus command requesting
a frequency change through byte 4 or through bytes 13 and
14, it must have previously sent a command selecting which
time-out stamp the Watchdog must perform to byte 12, or the
system self-recovery feature will not be applicable. Conse-
quently this device will change frequency, and then the
Watchdog timer starts timing. Meanwhile, the system BIOS is
running its operation with the new frequency. If this device
receives a new SMBus command to clear the bits originally
programmed in byte 12, bits(3:0) (reprogram to 0000) before
Watchdog times out, this device will keep operating in its
normal condition with the new selected frequency. If the
Watchdog times out the first time before the new SMBus repro-
grams byte 12, bits(3:0) to (0000), then this device will send
a low system reset pulse, on SRESET# (see byte 12, bit 7),
and changes the Watchdog alarm (byte 12, bit 4) status to “1”
then restarts the Watchdog timer. If the Watchdog times out
a second time, this device will send another low pulse on
SRESET#, will relatch original hardware strapping frequency
(or second-to-last software-selected frequency, see byte 12,
bit6) selection, set Watchdog alarm bit (byte 12, bit4) to “1,”
then start the Watchdog timer again. The above-described
sequence will keep repeating until the BIOS clears the SMBus
byte 12 bits(3:0). Once the BIOS sets byte 12 bits(3:0) = 0000,
the Watchdog timer is turned off and the Watchdog alarm bit
(byte 12, bit 4) is reset to “0.”
S y s te m ru n n in g w ith
o rig in a lly s e le c te d
fre q u e n c y v ia
h a rd w a re s tra p p in g .
F re q u e n c y w ill c h a n g e b u t S y s te m S e lf
R e c o v e ry n o t a p p lic a b le (n o tim e s ta m p
s e le c te d a n d b y te 1 2 , b it(3 :0 ) is s till =
"0 000 "
No
No
R e c e iv e F re q u e n c y
C h a n g e R e q u e s t v ia
S M B u s B y te 4 o r V ia D ia l-
a -fre q u e n c y ?
Yes
C h a n g e to a n e w
fre q u e n c y
Is S M B u s B y te 9 , tim e o u t
s ta m p e n a b le d - (b y te 1 2 , b it
(3 :0 ) 0 0 0 0 )?
1 ) S e n d a n o th e r 3 m S lo w p u ls e o n S R E S E T
2 ) R e la tc h o rig in a l h a rd w a re s tra p p in g s e le c tio n
fo r re tu rn to o rig in a l fre q u e n c y s e ttin g s .
3 ) S e t W D A la rm b it (b y te 1 2 , B it4 ) to " 1 "
4 ) S ta rt W D tim e r
Y es
S ta rt in te rn a l w a tc h d o g tim e r.
Y es
W a tc h D o g tim e o u t?
No
S M B u s b y te 9 tim e o u t
s ta m p d is a b le d , B y te
N o 1 2 , b it(3 :0 ) = (0 0 0 0 )?
1) Send S RES ET
p u ls e
2 ) S e t W D b it
( b y te 1 2 , b it4 ) to ’1 ’
3 ) S ta rt W D tim e r
Yes
W a tc h D o g tim e o u t?
No
Y es
S M B u s b y te 1 2 tim e
o u t s ta m p d is a b le d ?
No
Y es
T u rn o ff w a tc h d o g tim e r.
K e e p n e w fre q u e n c y s e ttin g . S e t W D a la rm
b it ( b y te 1 2 , b it 4 ) t o ’’0 ’
Document #: 38-07349 Rev. *A
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY28342.PDF ] | |
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