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PDF CY28343 Data sheet ( Hoja de datos )
| Número de pieza | CY28343 | |
| Descripción | Zero Delay SDR/DDR Clock Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY28343
Zero Delay SDR/DDR Clock Buffer
Features
• Phase-lock loop clock distribution for DDR and SDR
SDRAM applications
• One-single-end clock input to 6 pairs DDR outputs or
13 SDR outputs.
• External feedback pins FBIN_SDR/FBOUT_SDR are
used to synchronize the outputs to the clock input for
SDR.
• External feedback pins FBIN_SDR/FBOUT_SDR are
used to synchronize the outputs to the clock input for
DDR.
• SMBus interface enables/disables outputs.
• Conforms to JEDEC SDR/DDR specifications
• Low jitter, low skew
• 48 pin SSOP package
Table 1. Function Table
SELDDR_SDR#
1= DDR Mode
0 = SDRAM Mode
CLKIN
2.5V
Compatible
3.3V
Compatible
SDRAM(0:12)
OFF
Active
3.3V
Compatible
DDRT/C(0:5)
Active
2.5V
Compatible
OFF
FBIN_DDR
2.5V
Compatible
OFF
FBOUT_DDR
Active
2.5V
Compatible
OFF
FBIN_SDR FBOUT_SDR
OFF
OFF
Active
3.3V
Compatible
Active
3.3V
Compatible
Block Diagram
Pin Configuration[1]
SCLK
SDATA
Control
Logic
VDD_3.3V
CLKIN
FBIN_DDR
*SELDDR_SDR
FBIN_SDR
PLL
VDD_2.5V
FBOUT_DDR
DDRT(0:5)
DDRC(0:5)
VDD_3.3V
FBOUT_SDR
SDRAM(0:12)
VDD_3.3V
SDRAM0
SDRAM1
SDRAM2
SDRAM3
VSS
VDD_3.3V
SDRAM4
SDRAM5
CLKIN
SDRAM6
SDRAM7
VSS
VDD_3.3V
SDRAM8
SDRAM9
SDRAM10
SDRAM11
VSS
VDD_3.3V
SDRAM12
FBOUT_SDR
FBIN_SDR*
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note:
1. Pins marked with [*] have internal pull-down resistors. Pins marked with [**] have internal pull-up resistors.
48 SELDDR_SDR#*
47 FBIN_DDR*
46 FBOUT_DDR
45 VDD_2.5V
44 DDRT5
43 DDRC5
42 DDRT4
41 DDRC4
40 VSS
39 VDD_2.5
38 DDRT3
37 DDRC3
36 DDRT2
35 DDRC2
34 VSS
33 VDD_2.5V
32 DDRT1
31 DDRC1
30 DDRT0
29 DDRC0
28 VSS
27 VDD_3.3V
26 SCLK**
25 SDATA**
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07369 Rev. *A
Revised December 26, 2002
1 page  
Byte 2: Output Register (1 = Enable, 0 = Disable)[4]
Bit @Pup
71
Pin #
Reserved for device test.
Description
61
51
41
Select drive strength for SDR outputs. 1 = Low drive, 0 = High drive
Reserved
21 SDRAM12. 1 = Enable, 0 = Output disabled asynchronously in a low state
31
21
18 SDRAM11. 1 = Enable, 0 = Output disabled asynchronously in a low state
17 SDRAM10. 1 = Enable, 0 = Output disabled asynchronously in a low state
11
01
16 SDRAM9. 1 = Enable, 0 = Output disabled asynchronously in a low state
15 SDRAM8. 1 = Enable, 0 = Output disabled asynchronously in a low state
CY28343
Byte 3: Silicon Register (Read Only)
Bit @Pup Pin #
71
60
Vendor ID
1000 Cypress
50
40
30
Revision ID
20
10
00
Description
Document #: 38-07369 Rev. *A
Page 5 of 10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CY28343.PDF ] | |
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