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PDF CY62128B Data sheet ( Hoja de datos )
| Número de pieza | CY62128B | |
| Descripción | 128K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62128B
MoBL
128K x 8 Static RAM
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• 4.5V – 5.5V operation
www.DataSheet•4UC.cMoOmS for optimum speed/power
• Low active power
(70 ns, LL version, Commercial, Industrial)
— 82.5 mW (max.) (15 mA)
• Low standby power
(70 ns, LL version, Commercial, Industrial)
— 110 µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description[1]
The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE1),
an active HIGH Chip Enable (CE2), an active LOW Output
Enable (OE), and three-state drivers. This device has an
automatic power-down feature that reduces power
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE1) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
CCEE12
WE
OE
INPUT BUFFER
512x 256x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05300 Rev. *C
Revised February 14, 2005
1 page  
Switching Characteristics[7] Over the Operating Range
Parameter
Description
READ CYCLE
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
www.DataSheet4tLUZ.OcEom
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[8, 9]
CE1 LOW to Low Z, CE2 HIGH to Low Z[9]
CE1 HIGH to High Z, CE2 LOW to High Z[8, 9]
tPU CE1 LOW to Power-up, CE2 HIGH to Power-up
tPD CE1 HIGH to Power-down, CE2 LOW to Power-down
WRITE CYCLE[10]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z[9]
WE LOW to High Z[8, 9]
CY62128B
MoBL
62128B-55
Min. Max.
62128B-70
Min. Max.
Unit
55 70 ns
55 70 ns
5 5 ns
55 70 ns
20 35 ns
0 0 ns
20 25 ns
5 5 ns
20 25 ns
0 0 ns
55 70 ns
55 70 ns
45 60 ns
45 60 ns
0 0 ns
0 0 ns
45 50 ns
25 30 ns
0 0 ns
5 5 ns
20 25 ns
Switching Waveforms
Read Cycle No.1[12, 13]
ADDRESS
DATA OUT
tOHA
tAA
PREVIOUS DATA VALID
tRC
DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10.
The internal write
the transition of any
time of the memory is defined by the overlap
of these signals can terminate the write. The input
odfaCtaEs1eLt-OupWa,nCdEh2oHldIGtimHi,nagnsdhWouEldLbOeWre.feCrEen1caenddtWo tEhemleuasdt ibnegLeOdgWe
aonf dthCeEsi2gnHaIGl thHattoteinrmitiainteataeswtrhitee,warnitde.
11. No input may exceed VCC + 0.5V.
12. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
13. WE is HIGH for read cycle.
Document #: 38-05300 Rev. *C
Page 5 of 11
5 Page 
CY62128B
MoBL
Document History Page
Document Title: CY62128B MoBL 128K x 8 Static RAM
Document Number: 38-05300
REV. ECN NO.
Issue
Date
Orig. of
Change
Description of Change
** 116566 06/20/02 DSG Changed from Spec number: 38-00524 to 38-05300
*A 126601 06/09/03
JUI Changed CE to CE1 and added CE2 ≤ 0.3V in Data Retention Characteristics table
Removed these part numbers from Ordering Information table:
CY62128BLL-55ZC, CY62128BLL-55ZAC, CY62128BLL-55ZRC,
CY62128BLL-70ZAC, CY62128BLL-70ZRI, CY62128BLL-70ZRC
*B 239134
www.DataSheet4U*.Ccom 321335
See ECN
See ECN
AJU Added Thermal Resistance table
Added Automotive product information
AJU Added Pb-free package information
Document #: 38-05300 Rev. *C
Page 11 of 11
11 Page | ||
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| PDF Descargar | [ Datasheet CY62128B.PDF ] | |
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