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PDF CY62128 Data sheet ( Hoja de datos )
| Número de pieza | CY62128 | |
| Descripción | 128K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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fax id: 10721CY62128
PRELIMINARY
CY62128
Features
• 4.5V − 5.5V operation
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 330 mW (max.) (60 mA)
• Low standby power (70 ns, LL version)
— 110 µW (max.) (20 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down
Logic Block Diagram
128K x 8 Static RAM
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE1) and write enable (WE) inputs LOW and chip enable
two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through
I/O7) is then written into the location specified on the address
pins (A0 through A16).
Reading from the device is accomplished by taking chip en-
able one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY62128 is available in a standard 400-mil-wide SOJ,
525-mil wide (450-mil-wide body width) SOIC and 32-pin
TSOP type I.
Pin Configurations
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE1
CE2
WE
OE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
62128-1
I/O5
I/O6
I/O7
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Top View
SOJ / SOIC
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
TSOP I
Top View
(not to scale)
32 OE
31 A10
30 CE1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
62128-2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 1996 - Revised November 1996
1 page  
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]
ADDRESS
CE1
CE2
WE
DATA I/O
tSA
tAW
tWC
tSCE
tPWE
tSCE
tSD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14]
ADDRESS
CE1
tWC
tSCE
CE2
WE
tSCE
tAW
tSA tPWE
tHA
tHD
tHA
OE
DATA I/O
NOTE 15
tHZOE
tSD
DATAIN VALID
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
tHD
CY62128
62128-7
62128-8
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CY62128.PDF ] | |
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