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PDF CY62128BN Data sheet ( Hoja de datos )
| Número de pieza | CY62128BN | |
| Descripción | 1-Mbit (128K x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62128BN
MoBL®
1-Mbit (128K x 8) Static RAM
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
www.DataSheet4U.com
• 4.5V–5.5V operation
• CMOS for optimum speed/power
• Low active power
(70 ns Commercial, Industrial, Automotive-A)
— 82.5 mW (max.) (15 mA)
• Low standby power
(55/70 ns Commercial, Industrial, Automotive-A)
— 110 µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
• Available in Pb-free and non-Pb-free 32-pin (450
mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I
Functional Description[1]
The CY62128BN is a high-performance CMOS static RAM
organized as 128K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE1), an active
HIGH Chip Enable (CE2), an active LOW Output Enable (OE),
and tri-state drivers. This device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE1) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
CCEE12
WE
OE
INPUT BUFFER
128K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Pin Configuration
Top View
SOIC
NC 1
32 VCC
A16 2
31 A15
A14 3
30 CE2
I/O 0
A12 4
29 WE
A7 5
28 A13
I/O 1
A6 6
27 A8
A5 7
26 A9
I/O 2
A4 8
25 A11
A3 9
24 OE
I/O 3
A2 10
23 A10
A1 11
22 CE1
I/O 4
A0 12
21 I/O7
I/O0 13
20 I/O6
I/O 5
I/O1 14
19 I/O5
I/O2 15
18 I/O4
I/O 6
GGgGNnNcD 16
17 I/O3
I/O 7
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06498 Rev. *A
Revised August 3, 2006
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CY62128BN
MoBL®
Switching Characteristics[7] Over the Operating Range
Parameter
Description
READ CYCLE
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
www.DataSheet4tULZ.cOoEm
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[7, 9]
CE1 LOW to Low Z, CE2 HIGH to Low Z[9]
CE1 HIGH to High Z, CE2 LOW to High Z[8, 9]
tPU CE1 LOW to Power-up, CE2 HIGH to Power-up
tPD CE1 HIGH to Power-down, CE2 LOW to Power-down
WRITE CYCLE[10]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z[9]
WE LOW to High Z[8, 9]
CY62128BN-55
Min. Max.
CY62128BN-70
Min. Max.
Unit
55 70 ns
55 70 ns
5 5 ns
55 70 ns
20 35 ns
0 0 ns
20 25 ns
5 5 ns
20 25 ns
0 0 ns
55 70 ns
55 70 ns
45 60 ns
45 60 ns
0 0 ns
0 0 ns
45 50 ns
25 30 ns
0 0 ns
5 5 ns
20 25 ns
Switching Waveforms
Read Cycle No.1[11, 12]
ADDRESS
DATA OUT
tOHA
tAA
PREVIOUS DATA VALID
tRC
DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
11. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
12. WE is HIGH for read cycle.
Document #: 001-06498 Rev. *A
Page 5 of 12
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Package Diagrams (continued)
32-pin TSOP Type I (8 x 20 mm) (51-85056)
CY62128BN
MoBL®
www.DataSheet4U.com
51-85056-*D
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-06498 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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