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PDF STW81103 Data sheet ( Hoja de datos )
| Número de pieza | STW81103 | |
| Descripción | Multi-band RF frequency synthesizer | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STW81103
Multi-band RF frequency synthesizer with integrated VCOs
Features
■ Integer-N frequency synthesizer
www.DataSheet4U■.comDual differential integrated VCOs with
automatic center frequency calibration:
– 2500 - 3050 MHz (direct output)
– 4350 - 5000 MHz (direct output)
– 1250 - 1525 MHz (internal divider by 2)
– 2175 - 2500 MHz (internal divider by 2)
– 625 - 762.5 MHz (internal divider by 4)
– 1087.5 - 1250 MHz (internal divider by 4)
■ Excellent integrated phase noise
■ Fast lock time: 150µs
■ Dual modulus programmable prescaler
(16/17 or 19/20)
■ 2 programmable counters to achieve a
feedback division ratio from 256 to 65551
(prescaler 16/17) and from 361 to 77836
(prescaler 19/20).
■ Programmable reference frequency divider
(10 bits)
■ Phase frequency comparator and charge pump
■ Programmable charge pump current
■ Digital lock detector
■ Dual digital bus interface: SPI and I2C bus (fast
mode) with 3 bit programmable address
(1100A2A1A0)
■ 3.3 V power supply
■ Power down mode (hardware and software)
■ Small size exposed pad VFQFPN28 package
5 mm x 5 mm x 1.0 mm
■ Process: BICMOS 0.35 µm SiGe
Applications
■ 2.5G and 3G Cellular infrastructure equipment
■ CATV equipment
■ Instrumentation and test equipment
■ Other wireless communication systems
Description
The STMicroelectronics STW81103 is an
integrated RF synthesizer with voltage controlled
oscillators (VCOs). Showing high performance,
high integration, low power, and multi-band
performances, STW81103 is a low cost one chip
alternative to discrete PLL and VCOs solutions.
STW81103 includes an Integer-N frequency
synthesizer and two fully integrated VCOs
featuring low phase noise performance and a
noise floor of -155dBc/Hz. The combination of
wide frequency range VCOs (thanks to center-
frequency calibration over 32 sub-bands) and
multiple output options (direct output, divided by 2
or divided by 4) allows to cover the
625 MHz-762.5 MHz, the 1087.5 MHz-1525 MHz,
the 2175 MHz-3050 MHz and the
4350 MHz-5000 MHz bands.
The STW81103 is designed with
STMicroelectronics advanced 0.35 µm SiGe
process.
March 2008
Rev 3
1/53
www.st.com
1
1 page  
STW81103
List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. VCO A (direct output) closed loop phase noise at 2.775 GHz
(FSTEP=200 kHz; FPFD=200 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. VCO B (direct output) closed loop phase noise at 4.675 GHz
www.DataSheet4U(.cFoSmTEP=200 kHz; FPFD=200 kHz; ICP=3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.3876 GHz
(FSTEP=200 kHz; FPFD=400 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.3376 GHz
(FSTEP=200 kHz; FPFD=400 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. VCO A (div. by 4 output) closed loop phase noise at 693.8 MHz
(FSTEP=200 kHz; FPFD=800 kHz; ICP=1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1168.8 MHz
(FSTEP=200 kHz; FPFD=800 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. PFD frequency spurs (direct output; FPFD=200 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Settling time (final frequency=2.4 GHz; FPFD=400 kHz; ICP=2.5 mA) . . . . . . . . . . . . . . . 17
Figure 15. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19. VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 24. Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 25. Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 26. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 41
Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 42
Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 43
Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 43
Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 44
Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 44
Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 45
Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 46
Figure 36. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 37. Ping-pong architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 38. Application diagram with external VCO (LO output from STW81103) . . . . . . . . . . . . . . . . 49
Figure 39. Application diagram with external VCO (LO output from VCO) . . . . . . . . . . . . . . . . . . . . . 49
Figure 40. VFQFPN28 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5/53
5 Page 
STW81103
Electrical specifications
Table 5.
Symbol
Electrical specifications (continued)
Parameter
Condition
Min.
Charge pump
ICP
VOCP
ICP sink/source(3)
Output voltage compliance
range
www.DataSheet4U.com
VCOs
Spurious(4)
KVCOA VCOA sensitivity(5)
KVCOB VCOB sensitivity(5)
ΔTLK
VCTRL
Maximum temperature
variation for continuous
lock(5) (6)
VCOA pushing(5)
VCOB pushing(5)
VCO control voltage(5)
LO harmonic spurious(5)
IVCOA VCOA current consumption
IVCOB VCOB current consumption
IVCOBUF
IDIV2
IDIV4
VCO buffer consumption
Divider by 2 consumption
Divider by 4 consumption
LO output buffer
PLO Output level
RL Return loss
IOUTBUF Current consumption
3-bit programmable
Direct output (FPFD=200 kHz)
Divider by 2 (FPFD=400 kHz)
Divider by 4 (FPFD=800 kHz)
Lower frequency range
Intermediate frequency range
Higher frequency range
Lower frequency range
Intermediate frequency range
Higher frequency range
VCO A
VCO B
FVCO=2.8 GHz; amplitude[11]
FVCO=2.8 GHz; amplitude[00]
FVCO=4.7 GHz; amplitude[11]
FVCO=4.7 GHz; amplitude[00]
Matched to 50 ohms
DIV4 Buff
DIV2 Buff
Direct output
0.4
45
60
85
45
60
85
125
95
0.4
Typ. Max. Unit
5 mA
Vdd-0.3
V
-76 dBc
-82 dBc
-88 dBc
65 85 MHz/V
80 105 MHz/V
105 145 MHz/V
65 85 MHz/V
80 100 MHz/V
100 130 MHz/V
°C
°C
4 7 MHz/V
15 21 MHz/V
3V
-20 dBc
30 mA
16 mA
24 mA
13 mA
15 mA
17 mA
14 mA
0 dBm
15 dB
26 mA
23 mA
39 mA
11/53
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STW81103.PDF ] | |
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