PDF STW81100 Data sheet ( Hoja de datos )

Número de pieza	STW81100
Descripción	MULTI-BAND RF FREQUENCY SYNTHESIZER
Fabricantes	STMicroelectronics
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No Preview Available ! STW81100 MULTI-BAND RF FREQUENCY SYNTHESIZER WITH INTEGRATED VCOS DATASHEET 1 Features ■ Integer-N Frequency Synthesizer ■ Dual differential integrated VCOs with automatic center frequency calibration: – Direct Output: 3280 – 3900 MHz www.DataShee3t48U0.0co–m 4400 MHz – Internal divider by 2: 1640 – 1950 MHz 1900 – 2200 MHz – Internal divider by 4: 820 – 975 MHz 950 – 1100 MHz ■ Fast lock time: 150µs ■ Dual modulus prescaler (64/65) and 2 programmable counters to achieve a feedback division ratio from 4096 to 32767. ■ Programmable reference frequency divider (9 bits) ■ Phase frequency comparator and charge pump ■ Programmable charge pump current ■ Digital Lock Detector ■ I2C bus interface with 3 bit programmable address (1100A2A1A0) ■ 3.3V Power Supply ■ Power down mode ■ Small size exposed pad VFQFPN28 package 5x5x1.0mm ■ Process: BICMOS 0.35µm SiGe Figure 1. Package VFQFPN28 Table 1. Order Codes Part Number STW81100AT STW81100ATR Package VFQFPN28 VFQFPN28 in Tape & Reel tors (VCOs). Showing high performance, high integration, low power, and multi-band performances, STW81100 is a low cost one chip alternative to discrete PLL and VCOs solutions. STW81100 includes an Integer-N frequency syn- thesizer and two fully integrated VCOs featuring low phase noise performance and a noise floor of -153dBc/Hz. The combination of wide frequency range VCOs (thanks to center-frequency calibra- tion over 32 sub-bands) and multiple output op- tions (direct output, divided by 2 or divided by 4) allows to cover the 820MHz-1100MHz, the 1640MHz-2200MHz and the 3280MHz-4400MHz bands. The STW81100 is designed with STMicroelectron- ics advanced 0.35µm SiGe process. 2 Description The STMicroelectronics STW81100 is an integrat- ed RF synthesizer and voltage controlled oscilla- 3 Applications ■ Cellular 3G Infrastructure Equipment ■ Other Wireless Communication Systems April 2005 Rev. 2 1/23 1 page Table 6. Electrical Characteristcs (continued) CHARGE PUMP Symbol Parameter ICP ICP sink/source1 VOCP Output voltage compliance range Spurious2,3 Test Condition 3bit programmable Direct Output Divider by 2 VCOs www.DataSKhevecot4AU.coVmCOA sensitivity3 KvcoB VCOB sensitivity3 VCOA Pushing3 VCOB Pushing3 VCO control voltage Divider by 4 Sub-Band 00000 Sub-Band 01111 Sub-Band 11111 Sub-Band 00000 Sub-Band 01111 Sub-Band 11111 LO Harmonic Spurious VCO current consumption VCO buffer consumption IDIV2 DIVIDER by 2 consumption IDIV4 DIVIDER by 4 consumption LO OUTPUT BUFFER POUT Output level RL Return Loss ILOBUF Current Consumption Matched to 50ohm DIV4 Buff DIV2 Buff Direct Output EXTERNAL VCO (Test purpose only) fINVCO Frequency range PIN Input level VINDC DC Input level IEXTBUF Current Consumption VCO Internal Buffer STW81100 Min Typ Max Units 4 mA 0.4 Vdd-0.3 V -65 -54 dBc -70 -60 dBc -70 -66 dBc 85 105 135 MHz/V 55 70 95 MHz/V 35 50 65 MHz/V 60 75 100 MHz/V 35 45 60 MHz/V 20 25 35 MHz/V 7 10 MHz/V 9 14 MHz/V 0.4 3 V -20 dBc 25 mA 15 mA 18 mA 14 mA 0 dBm 15 dB 26 mA 23 mA 37 mA 3.28 0 2 15 4.4 GHz +6 dBm V mA 5/23 5 Page STW81100 where: – FVCO: output frequency of VCO. – P: modulus of dual modulus prescaler. – B: division ratio of the main counter. – A: division ratio of the swallow counter. – Fref: input reference frequency. – R: division ratio of reference counter. – N: division ratio of PLL For a correct work of the VCO divider, B must be strictly higher than A. A can take any value ranging from 0 to 63. The range of the N number can vary from 4096 to 32767. Figure 13. VCO Divider Diagram www.DataSheet4U.com VCOBUF- VCOBUF+ Prescaler 64/65 modulus 6 bit A counter To PFD 9 bit B counter 7.5 Phase frequency detector (PFD) The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function. Figure 6 is a simplified schematic of the PFD. Figure 14. PDF Diagram VDD Fref Fref VDD D FF R R D FF Delay ABL Up Down 11/23 11 Page

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