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PDF STW81102 Data sheet ( Hoja de datos )
| Número de pieza | STW81102 | |
| Descripción | Multi-band RF frequency synthesizer | |
| Fabricantes | STMicroelectronics | |
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STW81102
Multi-band RF frequency synthesizer with integrated VCOs
Feature summary
■ Integer-N Frequency Synthesizer
www.DataSheet4U■.comDual differential integrated VCOs with
automatic center frequency calibration:
– 3000 - 3620 MHz (Direct output)
– 4000 - 4650 MHz (Direct output)
– 1500 - 1810 MHz (Internal divider by 2)
– 2000 - 2325 MHz (Internal divider by 2)
– 750 - 905 MHz (Internal divider by 4)
– 1000 - 1162.5 MHz (Internal divider by 4)
■ Excellent integrated phase noise
■ Fast lock time: 150µs
■ Dual modulus programmable prescaler (16/17
or 19/20)
■ 2 programmable counters to achieve a
feedback division ratio from 256 to 65551
(prescaler 16/17) and from 361 to 77836
(prescaler 19/20).
■ Programmable reference frequency divider (10
bits)
■ Phase frequency comparator and charge pump
■ Programmable charge pump current
■ Digital Lock Detector
■ Dual Digital Bus Interface: SPI and I2C bus with
3 bit programmable address (1100A2A1A0)
■ 3.3V Power Supply
■ Power down mode (HW and SW)
■ Small size exposed pad VFQFPN28 package
5x5x1.0mm
■ Process: BICMOS 0.35µm SiGe
Order codes
Part number
STW81102AT
STW81102ATR
Temp range, °C
-40 to 85
-40 to 85
VFQFPN28
Applications
■ 2.5G and 3G Cellular Infrastructure Equipment
■ CATV Equipment
■ Instrumentation and Test Equipment
■ Other Wireless Communication Systems
Description
The STMicroelectronics STW81102 is an
integrated RF synthesizer with voltage controlled
oscillators (VCOs). Showing high performance,
high integration, low power, and multi-band
performances, STW81102 is a low cost one chip
alternative to discrete PLL and VCOs solutions.
STW81102 includes an Integer-N frequency
synthesizer and two fully integrated VCOs
featuring low phase noise performance and a
noise floor of -155dBc/Hz. The combination of
wide frequency range VCOs (thanks to center-
frequency calibration over 32 sub-bands) and
multiple output options (direct output, divided by 2
or divided by 4) allows to cover from 750MHz to
905MHz and 1000MHz to 1162.5MHz, from
1500MHz to 1810MHz and 2000MHz to
2325MHz, from 3000MHz to 3620MHz and
4000MHz to 4650MHz bands.
The STW81102 is designed with
STMicroelectronics advanced 0.35µm SiGe
process.
Package
VFQFPN28
VFQFPN28
Packing
Tray
Tape & Reel
June 2006
Rev 2
1/43
www.st.com
1
1 page  
STW81102
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
www.DataSheet4UF.ciogmure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCO A (Direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VCO B (Direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VCO A (Direct output) closed loop phase noise at 3.6GHz . . . . . . . . . . . . . . . . . . . . . . . . 14
VCO B (Direct output) closed loop phase noise at 4.3GHz . . . . . . . . . . . . . . . . . . . . . . . . 14
VCO A (Div. by 2 output) closed loop phase noise at 1.65GHz . . . . . . . . . . . . . . . . . . . . . 15
VCO B (Div. by 2 output) closed loop phase noise at 2.15GHz . . . . . . . . . . . . . . . . . . . . . 15
VCO A (Div. by 4 output) closed loop phase noise at 825MHz . . . . . . . . . . . . . . . . . . . . . 15
VCO B (Div. by 4 output) closed loop phase noise at 1.075GHz . . . . . . . . . . . . . . . . . . . . 15
PFD Frequency Spurs (Direct Output; FPFD=200KHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PFD Frequency Spurs (Div. by 2 Output; FPFD=400KHz) . . . . . . . . . . . . . . . . . . . . . . . . . 16
PFD Frequency Spurs (Div. by 4 Output; FPFD=800KHz) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reference Frequency Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VCO Divider Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VCO Sub-Bands Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Start and Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SPI Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Differential/single ended output network in the 3.0 - 4.65GHz range . . . . . . . . . . . . . . . . . 35
LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 36
Evaluation Board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 36
Differential/single ended output network in the 1.5 - 2.325GHz range . . . . . . . . . . . . . . . . 37
LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 37
Evaluation Board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . 38
LC lumped balun for the divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . 38
Evaluation Board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . 39
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
VFQFPN28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5/43
5 Page 
STW81102
Electrical specifications
Table 5.
Electrical characteristics (continued)
All the Electrical Specifications are intended at 3.3V supply Voltage.
Symbol
Parameter
Test conditions
Min Typ Max Unit
VCTRL
VCO A Pushing(5)
VCO B Pushing(5)
VCO control voltage(5)
LO Harmonic Spurious(5)
4 7 MHz/V
14 20 MHz/V
0.4 3 V
-20 dBc
IVCOA
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IVCOB
VCOA current consumption
VCOB current consumption
IVCOBUF
IDIV2
IDIV4
VCO buffer consumption
DIVIDER by 2 consumption
DIVIDER by 4 consumption
fVCO=3.3GHz ; amplitude [11]
fVCO=3.3GHz ; amplitude [00]
fVCO=4.3GHz ; amplitude [11]
fVCO=4.3GHz ; amplitude [00]
30
16
22
11
15
17
13
mA
mA
mA
mA
mA
mA
mA
LO OUTPUT BUFFER
PLO Output level
RL Return Loss(5)
IOUTBUF Current Consumption
Matched to 50ohm
DIV4 Buff
DIV2 Buff
Direct Output
0 dBm
15 dB
27 mA
23 mA
39 mA
EXTERNAL VCO (Test purpose only)
Frequency range
Input level
Current Consumption
VCO Internal Buffer
3.0 4.65 GHz
0 +6 dBm
15 mA
PLL MISCELLANEOUS
IPLL
Tlock
Current Consumption
Lock up time (5), (6)
Input Buffer, Prescaler, Digital
Dividers, misc.
25KHz PLL bandwidth; within
1 ppm of frequency error
12
150
mA
µs
1. In order to achieve best phase noise performance 1V peak level is suggested.
2. The frequency step is related to the PFD input frequency as follows:
- fstep = fPFD for Direct Output
- fstep = fPFD/2 for Divided by 2 Output
- fstep = fPFD/4 for Divided by 4 Output
3. see relationship between ICP and REXT in the Circuit Description section (Charge Pump)
4. The level of the spurs may change depending on PFD frequency, Charge Pump current, selected channel and PLL loop
BW.
5. Guaranteed by design and characterization.
6. Frequency jump from 2300 to 2150 MHz; it includes the time required by the VCO calibration procedure (7 fPFD cycles with
fPFD=400KHz).
11/43
11 Page | ||
| Páginas | Total 43 Páginas | |
| PDF Descargar | [ Datasheet STW81102.PDF ] | |
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