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PDF LPS200 Data sheet ( Hoja de datos )

Número de pieza LPS200
Descripción HIGH PERFORMANCE LOW NOISE PHEMT
Fabricantes Filtronic Compound Semiconductors 
Logotipo Filtronic Compound Semiconductors Logotipo



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No Preview Available ! LPS200 Hoja de datos, Descripción, Manual

FEATURES
1.0 dB Noise Figure at 18 GHz
10 dB Associated Gain at 18 GHz
Low DC Power Consumption
LPS200
HIGH PERFORMANCE LOW NOISE PHEMT
GATE
BOND
PAD (2X)
SOURCE
BOND
PAD (2x)
DRAIN
BOND
PAD (2X)
DESCRIPTION AND APPLICATIONS
DIE SIZE: 12.6X10.2mils (320x260 µm)
DIE THICKNESS: 3.9 mils (100 µm)
BONDING PADS: 3.3X2.6 mils (85x65 µm)
The LPS200 is an Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs)
Pseudomorphic High Electron Mobility Transistor (PHEMT), utilizing an Electron-Beam direct-
write 0.25 µm by 200 µm Schottky barrier gate. The recessed “mushroom” gate structure minimizes
parasitic gate-source and gate resistances. The epitaxial structure and processing have been
optimized for high dynamic range. The LPS200 also features Si3N4 passivation and is available in
various packages.
Typical applications are as low noise devices for both narrowband and broadband amplifiers.
ELECTRICAL SPECIFICATIONS @ TAmbient = 25°C
Parameter
Symbol
Test Conditions
Saturated Drain-Source Current
Noise Figure
Associated Gain at minimum NF
Maximum Drain-Source Current
Transconductance
Gate-Source Leakage Current
Pinch-Off Voltage
Thermal Resistivity
frequency=18 GHz
IDSS
NF
GA
IMAX
GM
IGSO
VP
ΘJC
VDS = 2 V; VGS = 0 V
VDS = 2 V; IDS = 25% IDSS
VDS = 2 V; IDS = 25% IDSS
VDS = 2 V; VGS = 1 V
VDS = 2 V; VGS = 0 V
VGS = -5 V
VDS = 2 V; IDS = 1 mA
Min Typ Max Units
15 25 50 mA
0.7 1.3 dB
9 10
dB
125 mA
50 70
mS
1 10 µA
-0.25 -0.8 -1.5 V
285 °C/W
Phone: (408) 988-1845
Fax: (408) 970-9950
http:// www.filss.com
Revised: 1/23/01

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