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PDF CY28347 Data sheet ( Hoja de datos )
| Número de pieza | CY28347 | |
| Descripción | Universal Single-chip Clock Solution | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY28347
Universal Single-chip Clock Solution
for VIA P4M266/KM266 DDR Systems
Features
• Supports VIA P4M266/KM266 chipsets
• Supports Pentium® 4, Athlon processors
• Supports two DDR DIMMS
• Provides
— Two different programmable CPU clock pairs
— Six differential DDR SDRAM pairs
— Two low-skew/low-jitter AGP clocks
— Six low-skew/low-jitter PCI clocks
— One 48M output for USB
— One programmable 24M or 48M for SIO
• Dial-a-Frequency and Dial-a-dB features
• Spread Spectrum for best electromagnetic interference
(EMI) reduction
• SMBus-compatible for programmability
• 56-pin SSOP and TSSOP packages
Table 1. Frequency Selection Table
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CPU
66.80
100.20
120.00
133.33
72.00
105.00
160.00
140.00
77.00
110.00
180.00
150.00
90.00
100.00
200.00
133.33
AGP
66.80
66.80
60.00
66.67
72.00
70.00
64.00
70.00
77.00
73.33
60.00
60.00
60.00
66.67
66.67
66.67
PCI
33.40
33.40
30.00
33.33
36.00
35.00
32.00
35.00
38.50
36.67
30.00
30.00
30.00
33.33
33.33
33.33
www.DataSheet4U.com Block Diagram
Pin Configuration[1]
XIN
XOUT
PCI_STP#
CPU_STP#
PD#
SDATA
SCLK
XTAL
FS0
PLL1
FS2
FS3 FS1
SMBus
PLL2
VDDR
REF0
SELP4_K7#
/2
REF(0:1)
VDDI
CPUCS_T
CPUCS_C
VDDC
CPUT/CPU0D_T
CPUC/CPU0D_C
VDDPCI
PCI(3:5)
PCI_F
MULTSEL
PCI2
PCI1
VDDAGP
AGP(0:1)
VDD48M
48M
24_48M
BUF_IN
SELSDR_DDR#
S2D
CONVERT
VDDD
FBOUT
DDRT(0:5)
DDRC(0:5)
*FS0/REF0
VSSR
XIN
XOUT
VDDAGP
*MODE/AGP0
*SELP4_K7#/AGP1
*PCI_STP#
VSSAGP
**FS1/PCI_F
PCI1
*MULTSEL/PCI2
VSSPCI
PCI3
PCI4
VDDPCI
PCI5
*CPU_STP#
VSS48M
**FS3/48M
**FS2/24_48M
VDD48M
VDD
VSS
IREF
*PD#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VTTPWRGD#/REF1
55 VDDR
54 VSSC
53 CPUT/CPUOD_T
52 CPUC/CPUOD_C
51 VDDC
50 VDDI
49 CPUCS_C
48 CPUCS_T
47 VSSI
46 FBOUT
45 BUF_IN
44 DDRT0
43 DDRC0
42 DDRT1
41 DDRC1
40 VDDD
39 VSSD
38 DDRT2
37 DDRC2
36 DDRT3
35 DDRC3
34 VDDD
33 VSSD
32 DDRT4
31 DDRC4
30 DDRT5
29 DDRC5
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07352 Rev. *C
Revised December 26, 2002
1 page  
CY28347
Table 6. Byte Read and Byte Write Protocol (continued)
10
11:18
19
20:27
28
29
Acknowledge from slave
Command Code - 8 bits “1xxxxxxx” stands for byte
operation bit[6:0] of the command code represents
the offset of the byte to be accessed
Acknowledge from slave
Data Byte from Master – 8 Bits
Acknowledge from slave
Stop
10
11:18
19
20
21:27
28
29
30:37
38
39
Acknowledge from slave
Command Code - 8 bits “1xxxxxxx” stands for byte
operation bit[6:0] of the command code represents
the offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data byte from slave - 8 bits
Not Acknowledge
Stop
Byte 0: Frequency Select Register
Bit @Pup Pin#
70
6 H/W Setting 21
5 H/W Setting 10
4 H/W Setting
1
30
www.DataSheet4U.com
2
1
0
H/W Setting
H/W Setting
H/W Setting
11
20
7
Name
FS2
FS1
FS0
Reserved
FS3
SELP4_K7#
Description
Reserved.
For Selecting Frequencies see Table 1.
For Selecting Frequencies see Table 1.
For Selecting Frequencies see Table 1.
If this bit is programmed to “1,” it enables WRITES to bits (6:4,1) for
selecting the frequency via software (SMBus)
If this bit is programmed to a “0” it enables only READS of bits
(6:4,1), which reflect the hardware setting of FS(0:3).
Reserved
For Selecting frequencies in Table 1.
Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.
Byte 1: CPU Clocks Register
Bit @Pup
70
Pin#
61
51
41
3 1 48,49
2 1 53,52
1 0 53,52
01
11
Name
SSMODE
SSCG
SST1
SST0
CPUCS_T/C_ EN#
CPUOD_T/C_EN#
CPUT/C_PD_CNTRL
MULT0
Description
0 = Down Spread. 1 = Center Spread. See Table 9.
1 = Enable (default). 0 = Disable
Select spread bandwidth. See Table 9.
Select spread bandwidth. See Table 9.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disable asynchronously
in a LOW state.
In K7 mode, this bit is ignored. In P4 mode, when PD# asserted
LOW, 0 = drive CPUT to 2xIref and CPUC LOW and
1 = three-state CPUT and CPUC.
Only For reading the hardware setting of the Pin11 MULT0 value.
Byte 2: PCI Clock Register
Bit @Pup
Pin#
70
61
10
51
Name
PCI_DRV
PCI_F
Description
PCI clock output drive strength 0 = Normal, 1 = increase the drive
strength 20%.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
Reserved, set = 1.
Document #: 38-07352 Rev. *C
Page 5 of 22
5 Page 
CY28347
AC Parameters (continued)
66 MHz
100 MHz
133 MHz
200 MHz
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Tr / Tf CPUCS_T/C Rise and 0.4 1.6 0.4 1.6 0.4 1.6 0.4 1.6 ns 5,10,21
Fall Times
VD Differential Voltage AC 0.4 Vp+ 0.4 Vp+ 0.4 Vp+ 0.4 Vp+ V 24
0.6V
0.6V
0.6V
0.6V
VX Differential Crossover 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD V 14
Voltage
DI–0.2 DI+0.2 DI–0.2 DI+0.2 DI–0.2 DI+0.2 DI–0.2 DI+0.2
AGP
TDC
AGP(0:2) Duty Cycle
45 55 45 55 45 55 45 55 % 5,6,10
TPeriod AGP(0:2) Period
15 16 15 16 15 16 15 16 ns 5,6,10
THIGH AGP(0:2) HIGH Time
5.25
5.25
5.25
5.25 ns 10,25
TLOW AGP(0:2) LOW Time
5.05
5.05
5.05
5.05 ns 10,18
Tr/Tf
AGP(0:2) Rise and Fall 0.4 1.6 0.4 1.6 0.4 1.6 0.4 1.6 ns 10,21
Times
TSKEW Any AGP to Any AGP
Clock Skew
250 250 250 250 ps 10,11,12
TCCJ AGP(0:2) Cycle-to-Cycle
500
500
500
500 ps 6,10,11,12
Jitter
PCI
TDC
PCI(_F,1:6) Duty Cycle 45 55 45 55 45 55 45 55 % 5,6,10
TPeriod PCI(_F,1:6) Period
30.0
30.0
30.0
30.0 ns 5,6,10
THIGH PCI(_F,1:6) HIGH Time 12.0 12.0 12.0 12.0 ns 10,25
TLOWwww.DataSheet4U.com
PCI(_F,1:6) LOW Time
12.0
12.0
12.0
12.0 ns 10,18
Tr/Tf
PCI(_F,1:6) Rise and Fall 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 10,21
Times
TSKEW Any PCI to Any PCI Clock
500
500
500
500 ps 10,11,12
Skew
TCCJ
PCI(_F,1:6)
Cycle-to-Cycle Jitter
500 500 500 500 ps 10,6,11,12
48 MHz
TDC
48-MHz Duty Cycle
45 55 45 55 45 55 45 55 % 5,6,10
TPeriod 48-MHz Period
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 5,6,10
Tr/Tf
48-MHz Rise and Fall
Times
1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 10,21
TCCJ 48-MHz Cycle-to-Cycle 500 500 500 500 ps 10,6,11,12
Jitter
24 MHz
TDC
24-MHz Duty Cycle
45 55 45 55 45 55 45 55 % 5,6,10
TPeriod 24-MHz Period
41.660 41.667 41.660 41.667 41.660 41.667 41.660 41.667 ns 5,6,10
Tr / Tf
24-MHz Rise and Fall
Times
1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 10,21
TCCJ 24-MHz Cycle-to-Cycle 500 500 500 500 ps 6,10,11,12
Jitter
Notes:
24. Measured at VX between the falling edge and the following rising edge of the signal.
25. Probes are placed on the pins, and measurements are acquired at 0.4V.
Document #: 38-07352 Rev. *C
Page 11 of 22
11 Page | ||
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