PDF CY28344 Data sheet ( Hoja de datos )

Número de pieza	CY28344
Descripción	FTG
Fabricantes	Cypress Semiconductor
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No Preview Available ! PRELIMINARY CY28344 FTG for Intel Pentium 4 CPU and Chipsets Features • Compatible to Intel® CK-Titan and CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel Brookdale (845) and Brookdale G Pentium® 4 Chipsets • Programmable clock output frequency with less than 1MHz increment • Integrated fail-safe Watchdog timer for system recovery • Automatically switch to HW-selected or SW-programmed clock frequency when Watchdog timer time-out • Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus byte Read/Write and block Read/Write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength support • Programmable output skew support • Power management control inputs • Available in 48-pin SSOP CPU 3V66 PCI REF 48M ×3 ×4 ×9 ×1 ×2 Block Diagram X1 X2 FS0:4 XTAL OSC PLL Ref Freq PLL 1 Divider Network www.DataSheet4U.com MULTSEL0 VTTPWRGD/PD# PLL2 SDATA SCLK SMBus Logic 2 VDD_REF REF_2X VDD_CPU CPU0:2, CPU0:2#, VDD_3V66 3V66_1:3 VDD_3V66 3V66_0/VCH_CLK VDD_PCI PCI_F0:1 PCI0:6 VDD_48MHz 48MHz 24_48MHz Pin Configuration[1] VDD_REF X1 X2 GND_REF ^FS0/PCI_F0 ^FS1/PCI_F1 VDD_PCI GND_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI GND_PCI PCI4 PCI5 PCI6 VDD_3V66 GND_3V66 3V66_1 3V66_2 3V66_3 RST# VDD_CORE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 SSOP-48 REF_2X/FS2^ CPU0 CPU0# VDD_CPU CPU1 CPU1# GND_CPU VDD_CPU CPU2 CPU2# MULTSEL0 IREF GND_CPU 48MHz/FS3^ 24_48MHz VDD_48MHz GND_48MHz 3V66_0/VCH_CLK/FS4^ VDD_3V66 GND_3V66 SCLK SDATA VTTPWRGD/PD#* GND_CORE RST# Note: 1. Signals marked with “” and “^,” respectively, have internal pull-up and pull-down resistors. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07113, Rev. A Revised December 26, 2002 1 page PRELIMINARY CY28344 Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bit 9 Write 10 Acknowledge from slave 11:18 Command Code – 8 bit “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 20:27 Data byte – 8 bits 28 Acknowledge from slave 29 Stop Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Byte Read Protocol Description Start Slave address – 7 bit Write Acknowledge from slave Command Code – 8 bit “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Data byte from slave – 8 bits Not acknowledge Stop Data Byte Configuration Map Data Byte 0 www.DataSheet4U.com Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Pin# -- -- -- -- -- Name SEL3 SEL2 SEL1 SEL0 FS_Override Bit 2 Bit 1 Bit 0 -- SEL4 -- Spread Spectrum Enable -- Reserved Description SW Frequency selection bits. See Table 4. 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings SW Frequency selection bits. See Table 4. 0 = OFF; 1 = Enabled Reserved Power On Default 0 0 0 0 0 0 0 0 Data Byte 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 40, 39 44, 43 47, 46 -- -- -- -- -- Name CPU2, CPU2# CPU1, CPU1# CPU0, CPU0# Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input Description (Active/Inactive) (Active/Inactive) (Active/Inactive) Latched FS[4:0] inputs. These bits are Read-only. Power On Default 1 1 1 X X X X X Document #: 38-07113, Rev. A Page 5 of 22 5 Page PRELIMINARY Data Byte 16 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# -- -- -- -- -- -- -- -- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Data Byte 17 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 www.DataSheet4U.com Bit 0 Pin# -- -- -- -- -- -- -- -- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description CY28344 Power On Default 0 0 0 0 0 0 0 0 Power On Default 0 0 0 0 0 0 0 0 Document #: 38-07113, Rev. A Page 11 of 22 11 Page

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