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PDF AS5C4008 Data sheet ( Hoja de datos )
| Número de pieza | AS5C4008 | |
| Descripción | 512K x 8 SRAM SRAM MEMORY ARRAY | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
SRAM
AS5C4008
512K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATION
• SMD 5962-95600
• SMD 5962-95613
• MIL STD-883
FEATURES
• High Speed: 17, 20, 25, 35 and 45ns
• High-performance, low power military grade device
• Single +5V ±10% power supply
• Easy memory expansion with CE\ and OE\ options
• All inputs and outputs are TTL-compatible
• Ease of upgradability from 1 Meg using the 32 pin
evolutionary version.
OPTIONS
MARKING
• Timing
15ns access (contact factory)
17ns access
20ns access
25ns access
35ns access
www.DataSheet4U.com 45ns access
• Operating Temperature Range
Military: -55oC to +125oC
Industrial: -40oC to +85oC
• Packages
Ceramic Dip (600 mil)
Ceramic Flatpack
Ceramic LCC
Ceramic SOJ
Ceramic LCC (contact factory)
• Options
2V data retention/ low power
-15
-17
-20
-25
-35
-45
XT
IT
CW
F
EC
ECJ
ECA
L
No. 112
No. 304
No. 209
No. 502
No. 208
NOTE: Not all combinations of operating temperature, speed, data retention and low
power are necessarily available. Please contact factory for availability of specific part
number combinations.
PIN ASSIGNMENT
(Top View)
32-Pin DIP (CW), 32-Pin LCC (EC)
32-Pin SOJ (ECJ)
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
Vss 16
32 Vcc
31 A15
30 A17
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
32-Pin Flat Pack (F)
A18 1 32 Vcc
A16 2 31 A15
A14 3 30 A17
A12
4 29
WE\
A7
5 28
A13
A6 6 27 A8
A5 7 26 A9
A4
8 25
A11
A3
9 24
OE\
A2 10 23 A10
A1 11 22 CE\
A0
12 21
I/O7
I/O0 13 20 I/O6
I/O1 14 19 I/O5
I/O2 15 18 I/O4
Vss 16 17 I/O3
32-Pin LCC (ECA)
GENERAL DESCRIPTION
The AS5C4008 is a 4 megabit monolithic CMOS SRAM,
organized as a 512K x 8.
The evolutionary 32 pin device allows for easy upgrades from
the 1 meg SRAM.
For flexibility in high-speed memory applications, ASI offers
chip enable (CE\) and output enable (OE\) capabilities. These
enhancements can place the outputs in High-Z for additional flexibil-
ity in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW. This allows systems
designers to meet low standby power requirements.
All devices operate from a single +5V power supply and all
inputs are fully TTL-Compatible.
AS5C4008
Rev. 5.5 12/01
1
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4 3 2 32 31 30
5 1 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/O 7
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1 page  
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................................... Vss to 3.0V
Input rise and fall times ....................................................... 3ns
Input timing reference levels ............................................ 1.5V
Output reference levels ..................................................... 1.5V
Output load ............................................... See Figures 1 and 2
SRAM
AS5C4008
Q
167 ohms
1.73V
Q
167 ohms
1.73V
C=30pF
C=5pF
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1. All voltages referenced to VSS (GND).
2. -2V for pulse width < 20ns
3. I is dependent on output loading and cycle rates.
CC
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable and write enable can initiate and
terminate a WRITE cycle.
13. Output enable (OE\) is inactive (HIGH).
14. Output enable (OE\) is active (LOW).
15. ASI does not warrant functionality nor reliability of any
product in which the junction temperature exceeds
150°C. Care should be taken to limit power to acceptable
levels.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
(L Version Only)
Chip Deselect to Data
Retention Time
CONDITIONS
CE\ > (Vcc -0.2V)
VIN > (Vcc -0.2V) or < 0.2V
SYMBOL
VDR
VCC = 2V ICCDR
MIN
2
tCDR
0
MAX
4.5
Operation Recovery Time
tR 10
UNITS
V
mA
ns
ms
NOTES
4
4, 11
AS5C4008
Rev. 5.5 12/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
MECHANICAL DEFINITION*
ASI Case #209 (Package Designator EC)
SMD 5962-95600, Case Outline Z
D1
SRAM
AS5C4008
A
D
E
L
e
b2
R
SYMBOL
A
A1
b2
D
D1
E
e
L
R
SMD SPECIFICATIONS
MIN MAX
0.080
0.100
0.006
0.054
0.022
0.028
0.815
0.835
0.740
0.760
0.440
0.460
0.050 BSC
0.100 REF
0.009 REF
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
A1
*All measurements are in inches.
AS5C4008
Rev. 5.5 12/01
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AS5C4008.PDF ] | |
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