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PDF AS5C4008 Data sheet ( Hoja de datos )
| Número de pieza | AS5C4008 | |
| Descripción | 512K x 8 SRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AS5C4008 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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512K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATION
• SMD 5962-95600
• SMD 5962-95613
• MIL STD-883
FEATURES
• High Speed: 12, 15, 17, 20, 25, 35 and 45ns
• High-performance, low power military grade device
• Single +5V ±10% power supply
• Easy memory expansion with CE\ and OE\ options
• All inputs and outputs are TTL-compatible
• Ease of upgradability from 1 Meg using the 32 pin
evolutionary version.
OPTIONS
MARKING
• Timing
12ns access
-12
15ns access
-15
17ns access
-17
20ns access
-20
25ns access
-25
35ns access
-35
45ns access
-45
• Operating Temperature Range
Military: -55oC to +125oC
XT
Industrial: -40oC to +85oC
IT
• Packages
Ceramic Dip (600 mil)
CW No. 112
Ceramic Flatpack
F No. 304
Ceramic LCC
EC No. 209
Ceramic SOJ
ECJ No. 502
• Options
2V data retention/ low power
L
NOTE: Not all combinations of operating temperature, speed, data retention and
low power are necessarily available. Please contact factory for availability of specific
part number combinations.
SRAM
AS5C4008
PIN ASSIGNMENT
(Top View)
32-Pin DIP (CW), 32-Pin LCC (EC)
32-Pin SOJ (ECJ)
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
Vss 16
32 Vcc
31 A15
30 A17
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
32-Pin Flat Pack (F)
A18 1 32 Vcc
A16 2 31 A15
A14 3 30 A17
A12
4 29
WE\
A7
5 28
A13
A6 6 27 A8
A5 7 26 A9
A4
8 25
A11
A3
9 24
OE\
A2 10 23 A10
A1 11 22 CE\
A0
12 21
I/O7
I/O0 13 20 I/O6
I/O1 14 19 I/O5
I/O2 15 18 I/O4
Vss 16 17 I/O3
GENERAL DESCRIPTION
The AS5C4008 is a 4 megabit monolithic CMOS SRAM, orga-
nized as a 512K x 8.
The evolutionary 32 pin device allows for easy upgrades from
the 1 meg SRAM.
For flexibility in high-speed memory applications, Micross of-
fers chip enable (CE\) and output enable (OE\) capabilities. These
enhancements can place the outputs in High-Z for additional flexibility
in system design.
Writing to these devices is accomplished when write enable
(WE\) and CE\ inputs are both LOW. Reading is accomplished when
WE\ remains HIGH and CE\ and OE\ go LOW. This allows systems
designers to meet low standby power requirements.
All devices operate from a single +5V power supply and all inputs
are fully TTL-Compatible.
AS5C4008
Rev. 6.4 01/10
1
For more products and information
please visit our web site at
www.micross.com
Micross Components reserves the right to change products or specifications without notice.
1 page  
AC TEST CONDITIONS
Input pulse levels ................................................ Vss to 3.0V
Input rise and fall times ................................................... 3ns
Input timing reference levels ......................................... 1.5V
Output reference levels .................................................. 1.5V
Output load ............................................ See Figures 1 and 2
SRAM
AS5C4008
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1. All voltages referenced to VSS (GND).
2. -2V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable and write enable can initiate and
terminate a WRITE cycle.
13. Output enable (OE\) is inactive (HIGH).
14. Output enable (OE\) is active (LOW).
15. ASI does not warrant functionality nor reliability of any
product in which the junction temperature exceeds
150°C. Care should be taken to limit power to accept-
able levels.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
(L Version Only)
Chip Deselect to Data
Retention Time
CONDITIONS
CE\ > (Vcc -0.2V)
VIN > (Vcc -0.2V) or < 0.2V
SYMBOL
VDR
VCC = 2V ICCDR
MIN
2
tCDR
0
MAX
4.5
Operation Recovery Time
tR 10
UNITS NOTES
V
mA
ns 4
ms 4, 11
AS5C4008
Rev. 6.4 01/10
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
SRAM
AS5C4008
MECHANICAL DEFINITION*
Micross Case #209 (Package Designator EC)
SMD 5962-95600, Case Outline Z
A
D1
D
E
L
e
b2
R
A1
NOTE: These dimensions are per the SMD. Micross’ package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
AS5C4008
Rev. 6.4 01/10
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AS5C4008.PDF ] | |
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