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PDF AS5C4009 Data sheet ( Hoja de datos )
| Número de pieza | AS5C4009 | |
| Descripción | 512K x 8 SRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AS5C4009 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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SRAM
AS5C4009
512K x 8 SRAM
Ultra Low Power SRAM
AVAILABLE AS MILITARY
SPECIFICATION
• SMD 5962-956131,2
• MIL STD-8831
PIN ASSIGNMENT
(Top View)
32-Pin DIP, 32-Pin SOJ
& 32-Pin TSOP
FEATURES
• Ultra Low Power with 2V Data Retention
(0.2mW MAX worst case Power-down standby)
• Fully Static, No Clocks
• Single +5V ±10% power supply
• Easy memory expansion with CE\ and OE\ options
• All inputs and outputs are TTL-compatible
• Three state outputs
• Operating temperature range:
Ceramic -55oC to +125oC & -40oC to +85oC
Plastic -40oC to +85oC3
1. Not applicable to plastic package
2. Applies to CW package only.
3. Contact factory for -55oC to +125oC
OPTIONS
MARKING
• Timing
55ns access
-554
70ns access
-70
85ns access
-85
100ns access
-100
• Packages
Ceramic Dip (600 mil)
CW No. 112
Ceramic SOJ5
ECJ No. 502
Plastic TSOP
DG No. 1002
• Options
2V data retention/very low power L
4. For DG package, contact factory
5. Contact Factory
NOTE: Not all combinations of operating temperature, speed, data retention and low power are
necessarily available. Please contact the factory for availability of specific part number combina-
tions.
Pin Name
WE\
CE\
OE\
A0 - A18
I/O1 - I/O8
Vcc
Vss
Function
Write Enable Input
Chip Select Input
Output Enable Input
Address Inputs
Data Inputs/Outputs
Power
Ground
For more products and information
please visit our web site at
www.micross.com
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/01 13
I/02 14
I/03 15
Vss 16
32 Vcc
31 A15
30 A17
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 I/08
20 I/07
19 I/06
18 I/05
17 I/04
GENERAL DESCRIPTION
The AS5C4009 is organized as 524,288 x 8 SRAM utilizing a
special ultra low power design process. Micross’ pinout adheres to the
JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32
pin version allows for easy upgrades from the 1 meg SRAM design.
For flexibility in memory applications, Micross offers chip enable
(CE\) and output enable (OE\) capabilities. These features can place
the outputs in High-Z for additional flexibility in system design.
This devices operates from a single +5V power supply and all
inputs and outputs are fully TTL-compatible.
Writing to these devices is accomplished when write enable
(WE\) and CE\ inputs are both LOW. Reading is accomplished when
WE\ remains HIGH and CE\ and OE\ go LOW. The device offers
a reduced power standby mode when disabled, by lowering VCC to
2V and maintaining CE\ = 2V. This allows system designers to meet
ultra low standby power requirements.
AS5C4009
Rev. 5.2 01/10
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load ......................................... See Figures 1
SRAM
AS5C4009
Q
501o6h7moshms
1.73V
C C==13000pFpF
Fig. 1 Output Load Equivalent
NOTES
1. Overshoot: Vcc +3.0V for pulse width < 20ms.
2. Undershoot: -3V for pulse width < 20ms.
3. ICC is dependent on output loading and cycle rates.
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE.
7. WE\ is HIGH for READ cycle.
8. Device is continuously selected. Chip enables and
output enables are held in their active state.
9. Address valid prior to, or coincident with, latest
occurring chip enable.
10. tRC = Read Cycle Time.
11. Chip enable and write enable can initiate and
terminate a WRITE cycle.
12. Output enable (OE\) is inactive (HIGH).
13. Output enable (OE\) is active (LOW).
14. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
15. All voltage referenced to Vss (GND).
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
VCC for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CONDITIONS
CE\ > (VCC - 0.2V) VCC = 2V
SYMBOL
VDR
ICCDR
VIN > (VCC - 0.2V) VCC = 3V ICCDR
tCDR
tR
MIN
2
0
5
MAX
100
200
UNITS
V
μA
μA
ns
ms
NOTES
4
4, 10
AS5C4009
Rev. 5.2 01/10
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
SRAM
AS5C4009
ORDERING INFORMATION
EXAMPLE: AS5C4009CW-55L/XT1
Device Number
AS5C4009
AS5C4009
AS5C4009
AS5C4009
Package
Type
CW
CW
CW
CW
Speed
ns
-55
-70
-85
-100
Options** Process
L /*
L /*
L /*
L /*
EXAMPLE: AS5C4009DG-70/IT2
Device Number
AS5C4009
AS5C4009
AS5C4009
AS5C4009
Package
Type
DG
DG
DG
DG
Speed
ns
-55
-70
-85
-100
Options** Process
L /*
L /*
L /*
L /*
EXAMPLE: AS5C4009ECJ-85L/883C1
Device Number
AS5C4009
AS5C4009
AS5C4009
AS5C4009
Package
Type
ECJ
ECJ
ECJ
ECJ
Speed
ns
-55
-70
-85
-100
Options** Process
L /*
L /*
L /*
L /*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
** OPTIONS
L = 2V Data Retention/Ultra Low Power
NOTES:
1. All CSOJ devices, please consult factory. Not all combinations of operating temperature,
speed, data retention and low power are necessarily available. Please contact the factory for
availability of specific part number combinations.
2. Plastic devices not available as 883. For XT or 55ns devices, contact factory.
AS5C4009
Rev. 5.2 01/10
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AS5C4009.PDF ] | |
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