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PDF ISL6269A Data sheet ( Hoja de datos )
| Número de pieza | ISL6269A | |
| Descripción | High-Performance Notebook PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
August 7, 2006
ISL6269A
FN9253.1
High-Performance Notebook PWM
Controller
The ISL6269A IC is a Single-Phase Synchronous-Buck
PWM controller featuring Intersil's Robust Ripple Regulator
(R3) technology that delivers truly superior dynamic
response to input voltage and output load transients.
Integrated MOSFET drivers and bootstrap diode result in
fewer components and smaller implementation area.
Intersil’s R3 technology combines the best features of fixed-
frequency PWM and hysteretic PWM while eliminating many
of their shortcomings. R3 technology employs an innovative
modulator that synthesizes an AC ripple voltage signal VR,
analogous to the output inductor ripple current. The AC
signal VR enters a window comparator where the lower
threshold is the error amplifier output VCOMP, and the upper
threshold is a programmable voltage reference VW, resulting
in generation of the PWM signal. The voltage reference VW
sets the steady-state PWM frequency. Both edges of the
PWM can be modulated in response to input voltage
transients and output load transients, much faster than
conventional fixed-frequency PWM controllers. Unlike a
conventional hysteretic converter, the ISL6269A has an error
amplifier that provides ±1% voltage regulation at the FB pin.
The ISL6269A has a 1.5ms digital soft-start and can be
started into a pre-biased output voltage. A resistor divider is
used to program the output voltage setpoint. The ISL6269A
can be configured to operate in continuous-conduction-
mode (CCM) or diode-emulation-mode (DEM), which
improves light-load efficiency. In CCM the controller always
operates as a synchronous rectifier however, when DEM is
enabled the low-side MOSFET is permitted to stay off,
blocking negative current flow into the low-side MOSFET
from the output inductor.
Pinout
ISL6269A (4x4 QFN)
TOP VIEW
16 15 14 13
VIN 1
12 PVCC
VCC 2
FCCM 3
GND
11 LG
10 PGND
EN 4
9 ISEN
5678
Features
• High performance R3 technology
• Fast transient response
• ±1% regulation accuracy: -10°C to +100°C
• Wide input voltage range: +7.0V to +25.0V
• Output voltage range: +0.6V to +3.3V
• Wide output load range: 0A to 25A
• Selectable diode emulation mode for increased light load
efficiency
• Programmable PWM frequency: 200kHz to 600kHz
• Pre-biased output start-up capability
• Integrated MOSFET drivers and bootstrap diode
• Internal digital soft-start
• Power good monitor
• Fault protection
- Undervoltage protection
- Soft crowbar overvoltage protection
- Low-side MOSFET rDS(on) overcurrent protection
- Over-temperature protection
- Fault identification by PGOOD pull down resistance
Applications
• PCI express graphical processing unit
• Auxiliary power rail
• VRM
• Network adapter
Ordering Information
PART
PKG.
PART NUMBER MARKING TEMP (°C) PACKAGE DWG. #
ISL6269ACRZ 6269ACRZ -10 to +100 16 Ld 4x4 QFN L16.4x4
(See Note)
(Pb-Free)
ISL6269ACRZ-T 6269ACRZ 16 Ld 4x4 QFN Tape and L16.4x4
(See Note)
Reel (Pb-Free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6269A
Electrical Specifications
PARAMETER
These specifications apply for VIN = 15V, TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V, PVCC = 5V (Continued)
SYMBOL
TEST CONDITIONS
MIN TYP
POWER GOOD
PGOOD Pull Down Impedance
PGOOD Leakage Current
PGOOD Maximum Sink Current (Note 3)
RPG_SS
RPG_UV
RPG_OV
RPG_OC
IPGOOD
PGOOD = 5mA Sink
PGOOD = 5mA Sink
PGOOD = 5mA Sink
PGOOD = 5V
80 95
53 63
26 32
- 0.1
- 5.0
PGOOD Soft-Start Delay
GATE DRIVER
UG Pull-Up Resistance
UG Source Current (Note 3)
UG Sink Resistance
UG Sink Current (Note 3)
LG Pull-Up Resistance
LG Source Current (Note 3)
LG Sink Resistance
LG Sink Current (Note 3)
UG to LG Deadtime
LG to UG Deadtime
BOOTSTRAP DIODE
Forward Voltage
Reverse Leakage
CONTROL INPUTS
EN High Threshold
EN Low Threshold
FCCM High Threshold
FCCM Low Threshold
EN Leakage
FCCM Leakage
PROTECTION
TSS EN High to PGOOD High
RUGPU
IUGSRC
RUGPD
IUGSNK
RLGPU
ILGSRC
RLGPD
ILGSNK
tUGFLGR
tLGFUGR
200mA Source Current
UG - PHASE = 2.5V
250mA Sink Current
UG - PHASE = 2.5V
250mA Source Current
LG - PGND = 2.5V
250mA Sink Current
LG - PGND = 2.5V
UG falling to LG rising, no load
LG falling to UG rising, no load
VF PVCC = 5V, IF = 2mA
IR VR = 25V
VENTHR
VENTHF
VFCCMTHR
VFCCMTHF
IENL
IENH
IFCCML
IFCCMH
EN = 0V
EN = 5.0V
FCCM = 0V
FCCM = 5.0V
2.20 2.75
- 1.0
- 2.0
- 1.0
- 2.0
- 1.0
- 2.0
- 0.5
- 4.0
- 21
- 14
- 0.58
- 0.2
2.0 -
--
2.0 -
--
- 0.1
- 0.1
- 0.1
- 2.0
ISEN OCP Threshold
ISEN Short-Circuit Threshold
UVP Threshold
OVP Rising Threshold
OVP Falling Threshold
OTP Rising Threshold (Note 3)
OTP Hysteresis (Note 3)
NOTE:
3. Guaranteed by characterization.
IOC
ISC
VUV
VOVR
VOVF
TOTR
TOTHYS
ISEN sourcing
ISEN sourcing
19 26
- 50
81 84
113 116
100 103
- 150
- 25
MAX UNIT
133 Ω
89 Ω
46 Ω
1.0 µA
- mA
3.30 ms
1.5 Ω
-A
1.5 Ω
-A
1.5 Ω
-A
0.9 Ω
-A
- ns
- ns
-V
- µA
-V
1.0 V
-V
1.0 V
1.0 µA
1.0 µA
1.0 µA
- µA
33 µA
- µA
87 %
119 %
106 %
- °C
- °C
5 FN9253.1
August 7, 2006
5 Page 
ISL6269A
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors constructed with reverse package
geometry are available. A capacitor dissipates heat as a
function of RMS current and frequency. Be sure that IPP is
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at FSW.
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 6 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as:
(
IMAX2
⋅
(D
–
D2))
+
⎛
⎝
x
⋅
IMAX2
⋅1--D--2--
⎞
⎠
IIN_RMS
=
----------------------------------------------------------------------------------------------------
IMAX
(EQ. 14)
Where:
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
D = ------V----O----U-----T-------
VIN ⋅ EFF
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0
x=1
x = 0.75
x = 0.50
x = 0.25
x=0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY CYCLE
1
FIGURE 6. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
VIN-VOUT across it. The preferred low-side MOSFET
emphasizes low rDS(on) when fully saturated to minimize
conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
PCON_LS ≈ ILOAD2 ⋅ rDS(on)_LS • (1 – D)
(EQ. 15)
For the high-side MOSFET, (HS), its conduction loss is
written as:
PCON_HS
=
IL
O
A
2
D
•
rD
S
(
o
n
)
_
H
S
•
D
(EQ. 16)
For the high-side MOSFET, its switching loss is written as:
PSW_HS
=
-V----I--N----•---I--V----A----L---L---E----Y-----•--T----O-----N----•---F----S----W--- + V-----I--N----•---I--P----E----A----K----•---T----O----F----F----•---F---S----W----
22
(EQ. 17)
Where:
- IVALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- TON is the time required to drive the device into
saturation
- TOFF is the time required to drive the device into cutoff
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
CBOOT
=
---------Q-----g---------
∆VBOOT
(EQ. 18)
Where:
- Qg is the total gate charge required to turn on the
high-side MOSFET
- ∆VBOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
11 FN9253.1
August 7, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL6269A.PDF ] | |
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