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PDF ISL6269 Data sheet ( Hoja de datos )
| Número de pieza | ISL6269 | |
| Descripción | Single Phase PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
June 14, 2005
ISL6269
FN9177.0
Single Phase PWM Controller for Mobile
Graphical Processing Unit (GPU)
The ISL6269 IC is a Single-Phase Synchronous-Buck PWM
controller featuring Intersil's Robust Ripple Regulator (R3)
technology that delivers truly superior dynamic response to
input voltage and output load transients. Integrated
MOSFET drivers, 5V LDO, and bootstrap diode result in
fewer components and smaller implementation area.
Intersil’s R3 technology combines the best features of fixed-
frequency PWM and hysteretic PWM while eliminating many
of their shortcomings. R3 technology employs an innovative
modulator that synthesizes an AC ripple voltage signal VR,
analogous to the output inductor ripple current. The AC
signal VR enters a hysteretic comparator where the lower
threshold is the error amplifier output VCOMP, and the upper
threshold is a programmable voltage reference VW, resulting
in generation of the PWM signal. The voltage reference VW
sets the steady-state PWM frequency. Both rising and falling
edges of the PWM are modulated, providing faster response
to input voltage transients and output load transients than
conventional fixed-frequency PWM controllers. Unlike a
conventional hysteretic converter, the ISL6269 has an error
amplifier that provides ±1% voltage regulation at the FB pin.
The ISL6269 has a 1.5ms digital soft-start and can be
started into a pre-biased output voltage. A resistor divider is
used to program the output voltage setpoint. The ISL6269
can be configured to operate in forced-continuous-
conduction-mode (FCCM) or in diode-emulation-mode
(DEM), which improves light-load efficiency. In FCCM the
controller always operates as a synchronous rectifier,
switching the low-side MOSFET regardless of the output
load, however with DEM enabled, the low-side MOSFET is
disabled preventing negative current flow from the output
inductor during low load operation. An audio filter prevents
the PWM switching frequency from entering the audible
spectrum due to extremely light load while in DEM.
A PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The ISL6269 features a unique
fault-identification capability that can drastically reduce
trouble-shooting time and effort. The pull-down resistance of
the PGOOD pin is 30Ω for an overcurrent fault, 60Ω for an
overvoltage fault, or 90Ω for either an undervoltage fault or
during soft-start. The overcurrent protection is accomplished
by measuring the voltage drop across the rDS(ON) of the
low-side MOSFET. A single resistor programs the
overcurrent and short-circuit points. Overvoltage and
undervoltage protection is monitored at the FB voltage
feedback pin.
Features
• High performance synthetic ripple regulation
• Extremely fast transient response
• External type-two loop compensation
• ±1% regulation accuracy: -10°C to +100°C
• Starts into a pre-biased output
• Wide input voltage range: +7.0V to +25.0V
• Wide output voltage range: +0.6V to +3.3V
• Wide output load range: 0A to 25A
• Programmable PWM frequency: 200kHz to 600kHz
• Power good monitor
• Fault identification by PGOOD pull down resistance
• Integrated MOSFET drivers with shoot-through protection
• Internal digital soft-start
• Internal 5V LDO regulator
• Configure forced continuous conduction or diode
emulation for increased light load efficiency
• PWM minimum frequency above audible spectrum
• Integrated boot-strap diode
• Low-side MOSFET rDS(ON) overcurrent protection
• Undervoltage protection
• Soft crowbar overvoltage protection
• Over-temperature protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• PCI express graphical processing unit
• Auxiliary power rail
• VRM
• Network adapter
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6269
Functional Pin Descriptions
GND Pin
Bottom terminal pad of QFN package
Signal common of the IC. Unless otherwise stated, signals
are referenced to the GND pin, not the PGND pin.
VIN Pin-1 (Input)
The VIN pin measures the converter input voltage with
respect to the GND pin. VIN is a required input to the R3
PWM modulator. The VIN pin is also the input source for the
integrated +5V LDO regulator.
VCC Pin-2 (Output)
The VCC pin is the output of the integrated +5V LDO
regulator, which provides the bias voltage for the IC. The
VCC pin delivers regulated +5V whenever the EN pin is
pulled above VENTHR. For best performance the LDO
requires at least a 1µF MLCC decouple capacitor to the
GND pin.
FCCM Pin-3 (Logic)
The FCCM pin configures the controller to operate in forced-
continuous-conduction-mode (FCCM) or diode-emulation-
mode (DEM.) DEM is disabled when the FCCM pin is pulled
above the rising threshold voltage VFCCMTHR, and DEM is
enabled when the FCCM pin is pulled below the falling
threshold voltage VFCCMTHF.
EN Pin-4 (Logic)
The EN pin is the on/off switch of the IC. When the EN pin is
pulled above the rising threshold voltage VENTHR, VCC will
ramp up and begin regulation. The soft-start sequence
begins once VCC ramps above the power-on reset (POR)
rising threshold voltage VCCTHR. When the EN pin is pulled
below the falling threshold voltage VENTHF, PWM
immediately stops and VCC decays below the POR falling
threshold voltage VCCTHF, at which time the IC turns off.
COMP Pin-5 (Signal)
The COMP pin is the output of the control-loop error
amplifier. Loop compensation components connect from the
COMP pin to the FB pin.
FB Pin-6 (Signal)
The FB pin is the inverting input of the control loop error
amplifier. The converter will regulate to 600mV at the FB pin
with respect to the GND pin. Scale the desired output
voltage to 600mV with a voltage divider network made from
resistors RTOP and RBOTTOM. Loop compensation
components connect from the FB pin to the COMP pin.
FSET Pin-7 (Signal)
The FSET pin programs the PWM switching frequency of the
converter. Connect a resistor RFSET and a 10nF capacitor
CFSET from the FSET pin to the GND pin.
VO Pin-8 (Input)
The VO pin makes a direct measurement of the converter
output voltage used exclusively by the R3 PWM modulator.
The VO pin should be connected to the top of feedback
resistor RTOP at the converter output. Refer to Figure 1,
Typical Application Schematic.
ISEN Pin-9 (Input)
The ISEN pin is the input to the overcurrent protection (OCP)
and short-circuit protection (SCP) circuits. Connect a resistor
RSEN between the ISEN pin and the PHASE pin. Select the
value of RSEN that will force the ISEN pin to source the ISEN
threshold current IOC when the peak inductor current
reaches the desired OCP setpoint. The SCP threshold
current ISC is fixed at twice the OCP threshold current IOC
PGND Pin-10
The PGND pin should be connected to the source of the low-
side MOSFET, preferably with an isolated path that is in
parallel with the trace connecting the LG pin to the gate of
the MOSFET. The PGND pin is an isolated path used
exclusively to conduct the turn-off transient current that flows
out the PGND pin, through the gate-source capacitance of
the low-side MOSFET, into the LG pin, and back to the
PGND pin through the pull-down resistance of the LG driver.
The adaptive shoot-through protection circuit, measures the
low-side MOSFET gate voltage with respect to the PGND
pin, not the GND pin.
LG Pin-11 (Output)
The LG pin is the output of the low-side MOSFET gate
driver. Connect to the gate of the low-side MOSFET.
PVCC Pin-12 (Input)
The PVCC pin is the input voltage for the low-side MOSFET
gate driver LG. Connect a +5V power source to the PVCC
pin with respect to the GND pin, a 1µF MLCC bypass
capacitor needs to be connected from the PVCC pin to the
PGND pin, not the GND pin. The VCC output may be used
for the PVCC input voltage source. Connect the VCC pin to
the PVCC pin through a low-pass filter consisting of a
resistor and the PVCC bypass capacitor. Refer to Figure 1,
Typical Application Schematic.
5 FN9177.0
June 14, 2005
5 Page 
ISL6269
Diode Emulation
Positive inductor current can flow from the source of the
high-side MOSFET or from the drain of the low-side
MOSFET. Negative inductor current flows into the drain of
the low-side MOSFET. When the low-side MOSFET
conducts positive inductor current, the phase voltage will be
negative with respect to the GND pin. Conversely, when the
low-side MOSFET conducts negative inductor current, the
phase voltage will be positive with respect to the GND pin.
Negative inductor current occurs when the output load
current is less than ½ the inductor ripple current.
The ISL6269 can be configured to operate in forced-
continuous-conduction-mode (FCCM) or in diode-emulation-
mode (DEM), which can improve light-load efficiency. In
FCCM, the controller always operates as a synchronous
rectifier, switching the low-side MOSFET regardless of the
polarity of the output inductor current. In DEM, the low-side
MOSFET is disabled during negative current flow from the
output inductor. DEM is permitted when the FCCM pin is
pulled low, and disabled when pulled high.
When DEM is permitted, the converter will automatically
select FCCM or DEM according to load conditions. If positive
PHASE pin voltage is measured for eight consecutive PWM
pulses, then the converter will enter diode-emulation mode
on the next PWM cycle. If a negative PHASE pin voltage is
measured, the converter will exit DEM on the following PWM
pulse. An audio filter is incorporated into the PWM
generation circuitry that prevents the switching frequency
from entering the audible spectrum at low load conditions.
Overcurrent and Short-Circuit Protection
When an OCP or SCP fault is detected, the ISL6269
overcurrent and short-circuit protection circuit will pull the
PGOOD pin low and latch off the converter. The fault will
remain latched until the EN pin is pulled below VENF or if the
voltage at the VIN pin is reduced to the extent that VCC has
fallen below the POR VCCF threshold. Selecting the
appropriate value of resistor RSEN programs the OCP
threshold. The resistor RSEN is connected from the ISEN pin
to the PHASE pin. The PHASE pin is connected to the drain
terminal of the low-side MOSFET.
The OCP circuit measures positive-flowing, peak-current
through the output inductor, not the DC current flowing from
the converter to the load. The low-side MOSFET drain
current is assumed to be equal to the positive output
inductor current when the high-side MOSFET is turn off.
Current briefly conducts through the low-side MOSFET body
diode until the LG driver goes high. The peak inductor
current develops a voltage across the rDS(ON) of the low-
side MOSFET just as if it were a discrete current-sense
resistor. An OCP fault will occur when the ISEN pin has
measured more than the OCP threshold current IOC, on
consecutive PWM pulses, for a period exceeding 20µs. It
does not matter how many PWM pulses are measured
during the 20µs period. If a measurement falls below IOC
before 20µs has elapsed, then the timer is reset to zero. An
SCP fault will occur when the ISEN pin has measured more
than the short-circuit threshold current ISC, in less than
10µs, on consecutive PWM pulses. The relationship
between ID and ISEN can be written as:
–ISEN • RSEN = –ID • rDS(ON)
(EQ. 3)
The value of RSEN can then be written as:
RSEN = ---I--F----L----+-----I----P--2------P---------•---OI--O---C-C----S----P----•---r--D----S----(--O-----N----)
(EQ. 4)
Where:
- RSEN (Ω) is the resistor used to program the over-
current setpoint
- ISEN is the current sense current that is sourced from
the ISEN pin
- IOC is the ISEN threshold current value sourced from the
ISEN pin that will activate the OCP circuit
- IFL is the maximum continuous DC load current
- IPP is the inductor peak-to-peak ripple current
- OCSP is the desired overcurrent setpoint expressed as
a multiplier relative to IFL
Overvoltage
When an OVP fault is detected, the ISL6269 overvoltage
protection circuit will pull the PGOOD pin low and latch off
the converter. The fault will remain latched until the EN pin is
pulled below VENF or if the voltage at the VIN pin is reduced
to the extent that VCC has fallen below the POR VCCF
threshold.
When the voltage at the FB pin relative to the GND pin, has
exceeded the rising overvoltage threshold VOVR, the
converter will latch off however, the LG driver output will stay
high, forcing the low-side MOSFET to pull down the output
voltage of the converter. The low-side MOSFET will continue
to pull down the output voltage until the voltage at the FB pin
relative to the GND pin, has decayed below the falling
overvoltage threshold VOVF, at which time the LG driver
output is driven low, forcing the low-side MOSFET off. The
LG driver output will continue to switch on at VOVR and
switch off at VOVF until the EN pin is pulled below VENF or if
the voltage at the VIN is reduced to the extent that VCC has
fallen below the POR VCCF threshold.
11 FN9177.0
June 14, 2005
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL6269.PDF ] | |
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