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PDF PI6CV855 Data sheet ( Hoja de datos )
| Número de pieza | PI6CV855 | |
| Descripción | PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory | |
| Fabricantes | Pericom Semiconductor Corporation | |
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PI6CV8551122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Product Features
PLL clock distribution optimized for SSTL_2 DDR SDRAM
applications.
Distributes one differential clock input pair to five differential
clock output pairs.
Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
Operates at AVDD = 2.5V for core circuit and internal PLL,
and VDDQ = 2.5V for differential output drivers
Available Package:
Plastic 28-pin TSSOP
Product Description
PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM
applications. This PLL Clock Buffer is designed for 2.5 VDDQ and
2.5V AVDD operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to five differential pairs of clock outputs
(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the
Analog Power input (AVDD). When the AVDD is strapped low, the
PLL is turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. In low power mode, PLL is turned OFF,
Y[0:4] and Y[0:4] outputs are 3-stated.
The PI6CV855 is able to track Spread Spectrum Clocking to reduce
EMI.
Block Diagram
CLK
CLK
FBIN
FBIN
AVDD
PLL
Logic
and
Test Ciruit
Pin Configuration
GND 1
28 Y4
Y0
Y0 2
27 Y4
Y0
Y0 3
26 VD D Q
Y1
VD D Q 4
25 GND
Y1
CLK 5
24 FBOUT
Y2 CLK 6 28-Pin 23 FBOUT
Y2
AVDD 7
L 22
VD D Q
Y3
AGND 8
21 FBIN
Y3
GND 9
20 FBIN
Y4
Y1 10
19 GND
Y4
Y1 11
18 VD D Q
VD D Q 12
17 Y3
Y2 13
16 Y3
Y2 14
15 GND
1 PS8545 06/20/01
1 page  
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
AC Specifications
Switching characteristics over recommended operating free-air temperature range, fCLK > 100 MHz (unless otherwise noted).
(See Figure 1 and 2)
Parameter
Description
Diagram
AVCC, VDDQ = 2.5V ±0.2V
Min.
Nom.
Max
Units
t(θ) Static phase offset(1)
Figure 4 50 0 50
tjit(cc)
tjit(per)
Cycle-to-cycle jitter
Period jitter
Figure 3
Figure 6
75
75
75
ps
75
tjit(hper)
Half-period jitter
Figure 7
100
100
tsl(i)
tsl(o)
Input clock slew rate(2)
Output clock slew rate(2)
Figure 8
Figure 8
1.0
1.0
2.0
V/ns
2.0
tsk(o)
Output clock skew
Figure 5
100 ps
The PLL on the PI6CV855 meets all the above parameters while supporting SSC synthesizers with the following parameters(3).
SSC modulation frequency
30.0 50.0 kHz
SSC clock input frequency deviation
0.00
0.50
%
PLL loop bandwidth
2 MHz
Phase angle
0.031 degrees
Notes:
1. Static Phase offset does not include jitter.
2. The slew rate is determined from the IBIS model with test load shown in Figure 1.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5 PS8545 06/20/01
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PI6CV855.PDF ] | |
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