PDF PI6CV857L Data sheet ( Hoja de datos )

Número de pieza	PI6CV857L
Descripción	PLL Clock Driver
Fabricantes	Pericom Semiconductor Corporation
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No Preview Available ! PI6CV857L1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 PLL Clock Driver for 2.5V DDR-SDRAM Memory Product Features PLL clock distribution optimized for Double Data Rate SDRAM applications. Distributes one differential clock input pair to ten differential clock output pairs. Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 Input PWRDWN: LVCMOS www.DataSheet4U.com Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers Available Packages: Plastic 48-pin TSSOP Block Diagram/Pin Configuration Product Description PI6CV857L PLL clock device is developed for registered DDR DIMM applicationsThisPLLClockBufferisdesignedfor2.5VDDQ and2.5V AVDD operation and differential data input and output levels. Package options include plastic Thin Shrink Small-Outline Package (TSSOP).The device is a zero delay buffer that distributes a differ- ential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V LVCMOS input (PWRDWN) and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off and the differential clock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection fre- quency that is below the operating frequency of the PLL, the device will enter a low power mode. An input frequency detection circuit will detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6CV857L clock driver uses the input clocks (CLK, CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor- mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). The PI6CV857L is also able to track Spread Spectrum Clocking for reduced EMI. CLK CLK FBIN FBIN PLL PWRDWN AV DD Powerdown and Test Logic Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT GND Y0 Y0 VD D Q Y1 Y1 GND GND Y2 Y2 VD D Q VD D Q CLK CLK VD D Q AV D D AGND GND Y3 Y3 VD D Q Y4 Y4 GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 48-Pin 39 11 A 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 GND Y5 Y5 VD D Q Y6 Y6 GND GND Y7 Y7 VD D Q PWRDWN FBIN FBIN VD D Q FBOUT FBOUT GND Y8 Y8 VD D Q Y9 Y9 GND 1 PS8543 06/11/01 1 page PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 AC Specifications Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 ) Parameter Description Diagram AVCC, VDDQ = 2.5V ±0.2V Min. Nom. Max Units tjit(cc) Cycle-to-cycle jitter see Figure 3 75 75 t(q) Static phase offset(1) see Figure 4 50 0 50 tsk(o) www.DataSheet4U.com tjit(per) Output clock skew Period jitter see Figure 5 see Figure 6 75 100 ps 75 tjit(hper) Half-period jitter see Figure 7 100 100 tsl(i) tsl(o) Input clock slew rate(2) Output clock slew rate(2) see Figure 8 see Figure 8 1.0 1.0 2.0 V/ns 2.0 The PLL on the PI6CV857L is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters(3). SSC modulation frequency 30.00 50.00 kHz SSC clock input frequency deviation 0.00 0.50 % PLL loop bandwidth 2 MHz Phase angle 0.031 degrees Notes: 1. Static Phase offset does not include Jitter. 2. The slew rate is determined from the IBIS model with test load shown in Figure1. 3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 5 PS8543 06/11/01 5 Page

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