PDF PI6CV857B Data sheet ( Hoja de datos )

Número de pieza	PI6CV857B
Descripción	1:10 PLL Clock Driver
Fabricantes	Pericom Semiconductor Corporation
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No Preview Available ! PI6CV857B 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory Product Features • Operating Frequency up to 200 MHz and exceeds PC2700 RDIMM specification • Distributes one differential clock input pair to ten differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 www.DataS•heeInt4pUu.tcoPmWRDWN: LVCMOS • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers • Packages (Pb-free and Green available): - 48-pin TSSOP Block Diagram CLK CLK FBIN FBIN PLL PWRDWN AVDD Powerdown and Test Logic Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT Product Description PI6CV857B PLL clock device is developed for registered DDR DIMM applicationsThisPLLClockBufferisdesignedfor2.5VDDQ and2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V LVCMOS input (PWRDWN) and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off and the differential clock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection fre- quency that is below the operating frequency of the PLL, the device will enter a low power mode. An input frequency detection circuit will detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6CV857B clock driver uses the input clocks (CLK, CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor- mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). The PI6CV857B is also able to track Spread Spectrum Clocking for reduced EMI. Pin Configurations: 48-pin TSSOP (package code A) GND Y0 Y0 VD D Q Y1 Y1 GND GND Y2 Y2 VD D Q VD D Q CLK CLK VD D Q AV D D AGND GND Y3 Y3 VD D Q Y4 Y4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 GND 47 Y5 46 Y5 45 VD D Q 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 38 VD D Q 37 PWRDWN 36 FBIN 35 FBIN 34 VD D Q 33 FBOUT 32 FBOUT 31 GND 30 Y8 29 Y8 28 VD D Q 27 Y9 26 Y9 25 GND 1 PS8639B 10/29/03 1 page PI6CV857B 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 AC Specifications Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 ) Parameter tjit(cc) t(θ) www.DataSheet4U.ctosmk(o) tjit(per) tjit(hper) tsl(i) tsl(o) VOX Description Cycle-to-cycle jitter Static phase offset(1) Output clock skew Period jitter Half-period jitter Input clock slew rate(2) Output clock slew rate(2) Output Differential Cross-Voltage Diagram see Figure 3 see Figure 4 see Figure 5 see Figure 6 see Figure 7 see Figure 8 see Figure 8 AVCC, VDDQ = 2.5V ±0.2V Min. Nom. Max –50 50 –50 0 50 75 –75 75 –100 100 1.0 4.0 1.0 2.0 (VDDQ/2) –0.1 (VDDQ/2) +0.1 Units ps V/ns V The PLL is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters(3). SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth Phase angle 30.00 0.00 2 50.00 –0.50 –0.031 kHz % MHz degrees Notes: 1. Static Phase offset does not include Jitter. 2. All AC parameters are measured using test load shown in Figure2. 3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 5 PS8639B 10/29/03 5 Page

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