PDF CY2210 Data sheet ( Hoja de datos )

Número de pieza	CY2210
Descripción	133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP/ USB/ and DRCG Support
Fabricantes	Cypress Semiconductor
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No Preview Available ! 0 CY2210 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support Features • Mixed 2.5V and 3.3V Operation • Compliant to Intel® CK133 (CY2210-3) & CK133W (CY2210-2) synthesizer and driver specification • Multiple output clocks at different frequencies — Four CPU clocks, up to 133 MHz — Eight synchronous PCI clocks, 1 free-running — Two CPU/2 clocks, at one-half the CPU frequency — Four AGP clocks at 66 MHz — Three synchronous APIC clocks, at 16.67 MHz — One USB clock at 48 MHz — Two reference clocks at 14.318 MHz • Spread Spectrum clocking — 32.5-kHz modulation frequency @ 133 MHz — 33.1-kHz modulation frequency @ 100 MHz for CY2210-02/03 — 33.4-kHz modulation frequency @ 100 MHz for CY2210-04 — EPROM programmable percentage of spreading. Default is –0.6%, which is recommended by Intel • Power-down features • Three Select inputs • Low-skew and low-jitter outputs • OE and Test Mode support • 56-pin SSOP package Benefits Usable with Pentium® II and Pentium® III processors Single-chip main motherboard clock generator — Driven together, support 4 CPUs and a chipset — Support for 4 PCI slots and chipset — Drives up to two main memory clock generators, includ- ing DRCG (CPUCLK/2) — Support for multiple AGP slots — Support multiprocessing systems — Supports USB frequencies and I/O chip Enables reduction of EMI in some systems Supports mobile systems Supports up to eight CPU clock frequencies Meets tight system timing requirements at high frequency Enables ATE and “bed of nails” testing Widely available, standard package enables lower cost Logic Block Diagram CPU_STOP XTALIN XTALOUT 14.318 MHz OSC. SEL1 SEL0 SEL133 SPREAD PCI_STOP PWR_DWN CPU PLL EPROM SYS PLL Divider, EPROM- ProgDelay and Stop Logic Intel and Pentium are registered trademarks of Intel Corporation. Pin Configuration SSOP Top View REFCLK [0–1] (14.318 MHz) VSSREF REFCLK0 REFCLK1 CPUCLK [0–3] VDDREF XTALIN CPUCLK/2 [0–1] (DRCG) XTALOUT VSSPCI PCICLK_F PCICLK_F (33.33 MHz) PCICLK1 VDDPCI PCICLK2 PCICLK [1–7] (33.33 MHz) APICCLK [0–2] (16.67 MHz) PCICLK3 VSSPCI PCICLK4 PCICLK5 AGPCLK [0–3] (66.67 MHz) VDDPCI PCICLK6 PCICLK7 USBCLK (48 MHz) VSSPCI VSSAGP AGPCLK0 AGPCLK1 VDDAGP VSSAGP AGPCLK2 AGPCLK3 VDDAGP SEL133 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDAPIC APICCLK2 APICCLK1 APICCLK0 VSSAPIC VDDCPU/2 CPUCLK/2 (DRCG) CPUCLK/2 (DRCG) VSSCPU/2 VDDCPU CPUCLK3 CPUCLK2 VSSCPU VDDCPU CPUCLK1 CPUCLK0 VSSCPU AVDD AVSS PCI_STOP CPU_STOP PWR_DWN SPREAD SEL1 SEL0 VDDUSB USBCLK VSSUSB Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07204 Rev. A Revised December 14, 2002 1 page CY2210 Switching Characteristics[4, 5] Over the Operating Range Parameter t1 t2 Output All CPU, CPU/2, APIC Description Output Duty Cycle[6] Rising Edge Rate Test Conditions t1A/t1B Between 0.4V and 2.0V t2 USB, REF Rising Edge Rate Between 0.4V and 2.4V t2 PCI, AGP Rising Edge Rate Between 0.4V and 2.4V t3 CPU, CPU/2, Falling Edge Rate Between 2.0V and 0.4V APIC t3 USB, REF Falling Edge Rate Between 2.4V and 0.4V t3 PCI, AGP Falling Edge Rate Between 2.4V and 0.4V t6 CPU CPU-CPU Skew Measured at 1.25V t7 CPU/2 CPU/2-CPU/2 Skew Measured at 1.25V t8 APIC APIC-APIC Skew Measured at 1.25V t9 AGP AGP-AGP Skew Measured at 1.5V t10 PCI PCI-PCI Skew Measured at 1.5V t11 CPU, AGP CPU-AGP Clock Skew CPU leads. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks t12 AGP, PCI AGP-PCI Clock Skew AGP leads. Measured at 1.5V t13 CPU, APIC CPU-APIC Clock Skew CPU leads. Measured at 1.25V t14 CPU, PCI CPU-PCI Clock Skew CPU leads. Measured at 1.25V clocks and 1.5V for 3.3V clocks CPU Cycle-Cycle Clock Jitter With all outputs running (CY2210-2) CPU Cycle-Cycle Clock Jitter With all outputs running (CY2210-3/-4) CPU Cycle-Cycle Clock Jitter With the USB output turned off (CY2210-3/-4) CPU/2 Cycle-Cycle Clock Jitter APIC Cycle-Cycle Clock Jitter USB Cycle-Cycle Clock Jitter AGP Cycle-Cycle Clock Jitter REF Cycle-Cycle Clock Jitter CPU, PCI Settle Time CPU and PCI clock stabilization from power-up Notes: 5. All parameters specified with loaded outputs. 6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. Min. 45 1.0 0.5 1.0 1.0 0.5 1.0 0 1.5 1.5 1.5 Max. 55 4.0 2.0 4.0 4.0 2.0 4.0 175 175 250 250 500 1.5 4.0 4 4 150 250 200 250 500 500 500 1000 3 Unit % V/ns V/ns V/ns V/ns V/ns V/ns ps ps ps ps ps ns ns ns ns ps ps ps ps ps ps ps ps ms Document #: 38-07204 Rev. A Page 5 of 10 5 Page

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