|
|
PDF CY2213 Data sheet ( Hoja de datos )
| Número de pieza | CY2213 | |
| Descripción | High Frequency Programmable PECL Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY2213 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
High Frequency Programmable PECL Clock Generator
Features
■ Jitter peak-peak (Typical) = 35 ps
■ LVPECL output
■ Default Select option
■ Serially configurable multiply ratios
■ Output edge rate control
■ 16-pin TSSOP
■ High frequency
■ 3.3 V operation
Logic Block Diagram
XIN
XOUT
OE
S
SER CLK
SER DATA
Xtal
Oscillator
CY2213
High Frequency Programmable PECL
Clock Generator
Benefits
■ High accuracy clock generation
■ One pair of differential output drivers
■ Phase-locked loop (PLL) multiplier select
■ 8-bit feedback counter and 6-bit reference counter for high
accuracy
■ Minimize electromagnetic interference (EMI)
■ Industry standard, low cost package saves on board space
For a complete list of related documentation, click here.
PLL CLK
xM CLKB
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07263 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 18, 2015
1 page  
CY2213
1 bit 7 bits
S Slave Address
Figure 4. CY2213 Transfer Format
1 bit 1 bit
R/W Ack
8 bits
1 bit 8 bits 1 bit 8 bits
Dummy Byte 0 Ack Dummy Byte 1 Ack Data 0
1 bit
Ack
Data 1
8 bits
Ack P
1 bit
Table 1. Serial Interface Address for the CY2213
A6 A5 A4 A3 A2 A1 A0 R/W
11001010
Table 2. Serial Interface Programming for the CY2213
Data0
Data1
Data2
b7
QCNTBYP
P<7>
Reserved
b6
SELPQ
P<6>
Reserved
b5
Q<5>
P<5>
Reserved
b4
Q<4>
P<4>
Reserved
b3
Q<3>
P<3>
Reserved
b2
Q<2>
P<2>
Reserved
b1
Q<1>
P<1>
Reserved
b0
Q<0>
P<0>
Reserved
To program the CY2213 using the two-wire serial interface, set
the SELPQ bit HIGH. The default setting of this bit is LOW. The
P and Q values are determined by the following formulas:
Pfinal = (P7..0 + 3) × 2
Qfinal = Q5..0 + 2.
PLL Frequency = Reference x P/Q = Output
If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value of
1. The default setting of this bit is LOW.
If the SELPQ bit is set LOW, the PLL multipliers are set using the
values in the Select Function Table.
CyberClocks™ has been developed to generate P and Q values
for stable PLL operation. This software is downloadable from
www.cypress.com
Reference
Figure 5. PLL Block Diagram
Q
VCO
P
PLL
Output
Document Number: 38-07263 Rev. *J
Page 5 of 16
5 Page 
CLK
CLKB
CLK
CLKB
Figure 13. Cycle-to-cycle Duty Cycle Error
Cycle i
Cycle i+1
tPW+,i+1
tPW+,i
tCYCLE,i+1
tCYCLE, i+1
tDC,ERR = tPW+,i – tPW+,i+1 over many consecutive cycles
Figure 14. Long-term Jitter
tmin
tmax
tJLT = tmax – tmin over many cycles
CY2213
Document Number: 38-07263 Rev. *J
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY2213.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY2210 | 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP/ USB/ and DRCG Support | Cypress Semiconductor |
| CY2213 | High Frequency Programmable PECL Clock Generator | Cypress Semiconductor |
| CY22150 | One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |