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PDF CY22150 Data sheet ( Hoja de datos )
| Número de pieza | CY22150 | |
| Descripción | One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY22150
One-PLL General-Purpose Flash-Programmable
and I2C Programmable Clock Generator
One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator
Features
■ Integrated phase-locked loop (PLL)
■ Commercial and industrial operation
■ Flash programmable
■ Field programmable
■ Two-wire I2C interface
■ Low skew, low jitter, high accuracy outputs
■ 3.3 V operation with 2.5 V output option
■ 16-pin TSSOP
Benefits
■ Internal PLL to generate six outputs up to 200 MHz. Able to
generate custom frequencies from an external crystal or
a driven source.
■ Performance guaranteed for applications that require an
extended temperature range.
■ Nonvolatile reprogrammable technology allows easy
customization, quick turnaround on design changes and
product performance enhancements, and better inventory
control. Parts can be reprogrammed up to 100 times, reducing
inventory of custom parts and providing an easy method for
upgrading existing designs.
■ The CY22150 can be programmed at the package level.
In-house programming of samples and prototype quantities is
available using the CY3672 Development Kit. Production
quantities are available through Cypress’s value added
distribution partners or by using third party programmers from
BP Microsystems™, HiLo Systems™, and others.
■ The CY22150 provides an industry standard interface for
volatile, system level customization of unique frequencies and
options. Serial programming and reprogramming allows quick
design changes and product enhancements, eliminates
inventory of old design parts, and simplifies manufacturing.
■ High performance suited for commercial, industrial,
networking, telecom, and other general purpose applications.
■ Application compatibility in standard and low power systems.
■ Industry standard packaging saves on board space.
Functional Description
For a complete list of related documentation, click here.
Selection Guide
Part Number Outputs
Input Frequency Range
CY22150KFZXC
6 8 MHz to 30 MHz (external crystal)
1 MHz to 133 MHz (driven clock)
Output Frequency Range
80 kHz to 200 MHz (3.3 V)
80 KHz to 166.6 MHz (2.5 V)
CY22150KFZXI
6 8 MHz to 30 MHz (external crystal) 80 kHz to 166.6 MHz (3.3 V)
1 MHz to 133 MHz (driven clock) 80 KHz to 150 MHz (2.5 V)
Specifications
Field programmable
Serially programmable
Commercial temperature
Field programmable
Serially programmable
Industrial temperature
Logic Block Diagram
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07104 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 4, 2016
1 page  
CY22150
Default Startup Condition for the CY22150
The default (programmed) condition of the device is generally set
by the distributor who programs the device using a customer
specific JEDEC file produced by CyClocksRT. Parts shipped
from the factory are blank and unprogrammed. In this condition,
all bits are set to 0, all outputs are three-stated, and the crystal
oscillator circuit is active.
While you can develop your own subroutine to program any or
all of the individual registers described in the following pages, it
may be easier to use CyClocksRT to produce the required
register setting file.
The serial interface address of the CY22150 is 69H. If there is a
conflict with any other devices in your system, then this can also
be changed using CyClocksRT.
Frequency Calculations and Register Definitions
using the I2C Interface
The CY22150 provides an industry standard serial interface for
volatile, in-system programming of unique frequencies and
options. Serial programming and reprogramming allows for quick
design changes and product enhancements, eliminates
inventory of old design parts, and simplifies manufacturing.
The I2C Interface provides volatile programming. This means
when the target system is powered down, the CY22150 reverts
to its pre-I2C state, as defined above (programmed or unpro-
grammed). When the system is powered back up again, the I2C
registers must be reconfigured again.
All programmable registers in the CY22150 are addressed with
eight bits and contain eight bits of data. The CY22150 is a slave
device with an address of 1101001 (69H).
Table 1 lists the I2C registers and their definitions. Specific
register definitions and their allowable values are listed below.
Reference Frequency
The REF can be a crystal or a driven frequency. For crystals, the
frequency range must be between 8 MHz and 30 MHz. For a
driven frequency, the frequency range must be between 1 MHz
and 133 MHz.
Using a Crystal as the Reference Input:
The input crystal oscillator of the CY22150 is an important
feature because of the flexibility it allows the user in selecting a
crystal as a REF source. The input oscillator has programmable
gain, allowing maximum compatibility with a reference crystal,
regardless of manufacturer, process, performance, and quality.
Programmable Crystal Input Oscillator Gain Settings:
The Input crystal oscillator gain (XDRV) is controlled by two bits
in register 12H and are set according to Table 2 on page 6. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
manufacturer), and the CapLoad setting during crystal startup.
Bits 3 and 4 of register 12H control the input crystal oscillator gain
setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The
setting is programmed according to Table 2 on page 6. All other
bits in the register are reserved and should be programmed as
shown in Table 3 on page 6.
Using an External Clock as the Reference Input:
The CY22150 also accepts an external clock as reference, with
speeds up to 133 MHz. With an external clock, the XDRV
(register 12H) bits must be set according to Table 4 on page 6.
Table 1. Summary Table – CY22150 Programmable Registers
Register
Description
D7 D6 D5 D4 D3 D2 D1 D0
09H CLKOE control
0
0
CLK6
CLK5
LCLK4 LCLK3 LCLK2 LCLK1
OCH DIV1SRC mux and
DIV1N divider
DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)
12H Input crystal oscillator
0
0
1 XDRV(1) XDRV(0) 0
0
0
drive control
13H Input load capacitor
control
CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad
(7) (6) (5) (4) (3) (2) (1) (0)
40H Charge pump and PB
41H counter
1
PB(7)
1
PB(6)
0
PB(5)
Pump(2) Pump(1) Pump(0)
PB(4)
PB(3)
PB(2)
PB(9)
PB(1)
PB(8)
PB(0)
42H PO counter, Q counter PO
Q(6)
Q(5)
Q(4)
Q(3)
Q(2)
Q(1)
Q(0)
44H Crosspoint switch
matrix control
CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1
for LCLK1 for LCLK1 for LCLK1 for LCLK2 for LCLK2 for LCLK2 for LCLK3 for LCLK3
45H CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2
for LCLK3 for LCLK4 for LCLK4 for LCLK4 for CLK5 for CLK5 for CLK5 for CLK6
46H
CLKSRC1 CLKSRC0
1
1
1
1
1
1
for CLK6 for CLK6
47H DIV2SRC mux and
DIV2N divider
DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)
Document Number: 38-07104 Rev. *P
Page 5 of 22
5 Page 
Figure 7. Definition for Timing on the Serial BUS
CY22150
Serial Bus specifications
Parameter
fSCLK
tHD:STA
tLOW
tHIGH
tSU:STA
tDH
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tBUF
Frequency of SCLK
Description
Hold time START condition
Low period of the SCK clock
High period of the SCK clock
Setup time for a repeated START condition
Data hold (SCLK LOW to data transition)
Data hold time
Data setup time
Rise time
Fall time
Setup time for STOP condition
Bus-free time between STOP and START conditions
Min Max Unit
– 400 kHz
0.6 – s
1.3 – s
0.6 – s
0.6 – s
100 – ns
100 – ns
100 – ns
– 300 ns
– 300 ns
0.6 – s
1.3 – s
Document Number: 38-07104 Rev. *P
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY22150.PDF ] | |
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