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PDF LT3641 Data sheet ( Hoja de datos )

Número de pieza LT3641
Descripción Dual Monolithic Buck Regulator
Fabricantes Linear 
Logotipo Linear Logotipo



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LT3641
Dual Monolithic Buck
Regulator with Power-On
Reset and Watchdog Timer
FEATURES
DESCRIPTION
n High Voltage Buck Regulator:
4V to 42V Operating Range
1.3A Output Current
n Input Transient Protection to 55V
n Low Voltage Synchronous Buck Regulator:
2.5V to 5.5V Input Voltage Range
1.1A Output Current
n Synchronizable, Adjustable 350kHz to 2.5MHz
Switching Frequency
n Programmable Power-On Reset Timer
n Programmable Window Mode Watchdog Timer
n Typical Quiescent Current: 290μA
n Short-Circuit Robust
n Programmable Soft-Start
n Low Shutdown Current: IQ < 1μA
n Thermal Shutdown
n Available in Thermally Enhanced 28-Lead
(4mm × 5mm) QFN and 28-Lead TSSOP Packages
APPLICATIONS
n Industrial Power Supplies
n Automotive Electronic Control Units
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
The LT®3641 is a dual channel, current mode monolithic buck
switching regulator with a power-on reset and a watchdog
timer. Both regulators are synchronized to a single oscillator
with an adjustable frequency (350kHz to 2.5MHz). At light
loads, both regulators operate in low ripple Burst Mode®
to maintain high efficiency and low output ripple.
The high voltage channel is a nonsynchronous buck with
an internal 2.4A top switch that operates from an input
of 4V to 42V and input transient protection to 55V. The
low voltage channel operates from an input of 2.5V to
5.5V. Internal synchronous power switches provide high
efficiency without the need of external Schottky diode.
Both channels have cycle-by-cycle current limit, providing
protection against shorted outputs.
The power-on reset and watchdog timeout periods are
both adjustable using external capacitors. The window
mode watchdog timer flags when the μP pulses group
too close together or too far apart.
The LT3641 is available in a 28-pin 4mm × 5mm QFN
package and 28-pin TSSOP package. Both packages have
an exposed pad for low thermal resistance.
TYPICAL APPLICATION
2MHz 5V/0.8A and 3.3V/0.5A Step Down Regulators
VIN
7V TO 42V*
VOUT1
100k
μP
0.22μF
10μF
EN/UVLO VIN SW
SYNC
WDE
PGOOD2
BST SW1
DA
FB1
100k
RST1
RST2
WDO
WDI
LT3641
VIN2
EN2
SW2
1.5nF
CWDT
FB2
CPOR RT GND SS2 SS1
1.5nF
32.4k
1nF
1nF
4.7μH
301k
100k
2.2μH
226k
49.9k
3641 TA01a
VOUT1
5V/0.8A
22μF
VOUT2
3.3V/0.5A
22μF
* FOR INPUT VOLTAGES ABOVE 42V RESTRICTIONS APPLY
HV Channel Efficiency,
2MHz, VOUT1 = 5V
90
VIN = 12V
85
80
75
70
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
VOUT1 CURRENT (A)
3641 TA01b
LV Channel Efficiency,
2MHz, VOUT2 = 3.3V
95
90 VIN2 = 5V
85
80
75
70
0
0.2 0.4 0.6 0.8 1.0 1.2
VOUT2 CURRENT (A)
3641 TA01c
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LT3641 pdf
LT3641
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
HV Channel Efficiency
(2MHz, VOUT1 = 3.3V)
90
85 VIN = 12V
VIN = 16V
80
VIN = 24V
75
70
0
0.2 0.4 0.6 0.8 1.0 1.2
VOUT1 CURRENT (A)
3641 G01
LV Channel Efficiency
(2MHz, VOUT2 = 1.8V)
90
VIN2 = 3.3V
85
VIN2 = 5V
80
75
70
0
0.2 0.4 0.6
VOUT2 CURRENT (A)
0.8 1.0
3641 G04
HV Channel Efficiency
(2MHz, VOUT1 = 5V)
95
90
85
80
75
70
65
0
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VOUT1 CURRENT (A)
3641 G02
Quiescent Current vs VIN
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
10 20 30
VIN VOLTAGE (V)
40
3641 G05
LV Channel Efficiency
(2MHz, VOUT2 = 1.2V)
90
85
VIN2 = 3.3V
80
VIN2 = 5V
75
70
0
0.2 0.4 0.6
VOUT2 CURRENT (A)
0.8 1.0
3641 G03
Quiescent Current vs Temperature
350
300
250
200
150
100
50
0
–50
0 50 100
TEMPERATURE (°C)
150
3641 G06
FB1 Voltage vs Temperature
1.40
1.35
1.30 REGULATION
1.25
1.20
RST1 THRESHOLD
1.15
1.10
1.05
1.00
–50
0 50 100
TEMPERATURE (°C)
150
3641 G07
FB1 Voltage vs SS1
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
0.5 1.0 1.5
SS1 VOLTAGE (V)
2.0
3641 G08
FB2 Voltage vs Temperature
0.70
0.65
0.60 REGULATION
RST2 THRESHOLD
0.55
0.50
0.45
–50
0 50 100
TEMPERATURE (°C)
150
3641 G09
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LT3641 arduino
LT3641
OPERATION
when the VIN2 pin voltage is above 2.3V, and the EN2 pin
is above its threshold. The internal top power MOSFET is
turned on each cycle at the beginning of each oscillator
cycle, and turned off when the current flowing through
the top MOSFET reaches a level determined by the voltage
at the VC2 node. An error amplifier measures the output
voltage through an external resistor divider tied to the FB2
pin and servos the VC2 node. The reference of the error
amplifier is determined by the lower of the internal 600mV
reference and the voltage at the SS2 pin.
While the top MOSFET is off, the bottom MOSFET is
turned on in an oscillator cycle until the inductor current
starts to reverse. If the inductor current is higher than the
valley current limit at the beginning of an oscillator cycle,
the bottom MOSFET will remain on and prevent the top
MOSFET from turning on until the overcurrent situation
clears, limiting inductor current in shorted output fault.
An internal regulator provides power to the control circuitry.
The regulator draws most power from the VIN2 pin and a
small portion of power from the VIN pin when the VIN2 pin
voltage is higher than 3V. If the voltage at VIN2 pin is lower
than 3V, the regulator draws all power from the VIN pin.
The EN/UVLO pin is used to put the LT3641 in shutdown,
reducing the input current to less than 1μA. The accurate
1.26V threshold of the EN/UVLO pin provides a program-
mableVIN undervoltagelockoutthroughanexternalresistor
divider tied to the EN/UVLO pin. A 2μA hysteresis current
on the EN/UVLO pin prevents switching noise from shut-
ting down the LT3641.
The LT3641 has an overtemperature protection feature
which disables switching in both channels when the junc-
tion temperature exceeds the overtemperature threshold.
Junction temperature will exceed the maximum operating
junction when overtemperature protection is active.
Internal 2μA current sources charge the SS1 pin and the SS2
pin up to about 2V. Soft-start or output voltage tracking of
the two channels can be independently implemented with
capacitors from the SS1 pin and the SS2 pin to ground. Any
undervoltage condition on the VIN pin triggers an internal
latch that discharges the SS1 pin to below 100mV before
it is released. If the EN2 pin goes below its threshold,
or the VIN2 voltage falls below 2.2V, the SS2 pin will be
discharged to below 100mV before it is released.
To optimize efficiency, the LT3641 switches to low ripple
Burst Mode operation in light load situations. Between
switching pulses, control-circuitry current is minimized.
A power good comparator with 40mV of hysteresis trips
when the low voltage channel is enabled and the FB2 pin
is above 550mV. The PGOOD2 pin is an open-drain output
that is pulled low when both the outputs are in regulation.
Power-On Reset and Watchdog Timer
The LT3641 includes one power-on reset timer for each
buck regulator and one common watchdog timer. Power-
on reset and watchdog timers are both adjustable using
external capacitors. Operation can be best understood by
referring to the Timing Diagram.
The RST1, RST2 and WDO pins are all open-drain outputs
with weak internal pull-ups to about 2V. The RST1 and RST2
pins are pulled low when the LT3641 is enabled and VIN is
above 3.6V. Once the FB1 pin rises above 1.165V, the high
voltage channel reset timer is started and RST1 is released
after the reset timeout period. The low voltage channel reset
timer is started once the FB2 pin rises above 550mV, and
releases RST2 after the reset timeout period.
The watchdog circuit monitors a μP’s activity. As soon as
RST2 is released, a delay timer is started. The watchdog
timer is started after the delay timer times out. The LT3641
implements windowed watchdog function for higher sys-
tem reliability. The watchdog timer detects falling edges
on the WDI pin. If the falling edges are grouped too close
together or too far apart, the WDO pin is pulled down and
the reset timer is started. When the reset timer times out,
WDO is released and the watchdog timer is again started
after the delay period.
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