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PDF SI53313 Data sheet ( Hoja de datos )
| Número de pieza | SI53313 | |
| Descripción | DUAL 1:5 LOW-JITTER ANY-FORMAT BUFFER/LEVEL TRANSLATOR | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si53313
DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL
TRANSLATOR (<1.25 GHZ)
Features
2 independent banks of 5x
Output clock division: /1, /2, /4 (dc to
differential outputs
725 MHz for /2 and /4)
Ultra-low additive jitter: 45 fs rms
Wide frequency range:
Independent VDD and VDDO:
1.8/2.5/3.3 V
dc to 1.25 GHz
Excellent power supply noise
Any-format input with pin selectable rejection (PSRR)
output formats: LVPECL, Low Power Small size: 44-QFN (7 mm x 7 mm)
LVPECL, LVDS, CML, HCSL,
RoHS compliant, Pb-free
LVCMOS
Industrial temperature range:
Asynchronous output enable
–40 to +85 °C
Low output-output skew: <70 ps
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Ordering Information:
See page 27.
Pin Assignments
Si53313
Description
DIVA 1
33 DIVB
The Si53313 is an ultra low jitter dual 1:5 differential buffer with pin-selectable
SFOUTA[1] 2
SFOUTA[0] 3
32 SFOUTB[1]
31 SFOUTB[0]
output clock signal format and divider selection. The Si53313 utilizes Silicon
Q2 4
30 Q7
Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz
with guaranteed low additive jitter, low skew, and low propagation delay variability.
Q2
GND
Q1
5
6
7
GND
PAD
29 Q7
28 NC
27 Q8
The Si53313 features minimal cross-talk and provides superior supply noise
Q1 8
Q0 9
26 Q8
25 Q9
rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
Q0 10
NC 11
24 Q9
23 NC
without the need for external circuitry.
Functional Block Diagram
Patents pending
VREF
CLK0
CLK0
Vref
Generator
Power
Supply
Filtering
DivA
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q 4
CLK1
CLK1
DivB
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q5, Q 6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Rev. 1.0 12/15
Copyright © 2015 by Silicon Laboratories
Si53313
1 page  
Si53313
Table 5. Output Characteristics (Low Power LVPECL)
(VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Output DC Common VCOM RL = 100 across Qn and Qn VDDOX – 1.895
Mode Voltage
Single-Ended
Output Swing
VSE RL = 100 across Qn and Qn
0.20
Typ
0.60
Max
Unit
VDDOX – 1.275 V
0.85 V
Table 6. Output Characteristics—CML
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Symbol
VSE
Test Condition
Terminated as shown in Figure 9
(CML termination).
Min
200
Typ Max Unit
400 550
mV
Table 7. Output Characteristics—LVDS
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(VDDO = 2.5 V or
3.3V)
Output Common
Mode Voltage
(VDDO = 1.8 V)
Symbol
VSE
VCOM1
VCOM2
Test Condition
RL = 100 Ω across QN and QN
VDDOX = 2.38 to 2.63 V, 2.97 to
3.63 V, RL = 100 Ω across QN
and QN
VDDOX = 1.71 to 1.89 V,
RL = 100 Ω across QN
and QN
Min
200
1.10
0.85
Typ Max
— 490
1.25 1.35
0.97 1.25
Unit
mV
V
V
Table 8. Output Characteristics—LVCMOS
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Output Voltage High
VOH
0.75 x VDDOX
—
—
Output Voltage Low
VOL
— — 0.25 x VDDOX
*Note: IOH and IOL per the Output Signal Format Table for specific VDDOX and SFOUTx settings.
Unit
V
V
Rev. 1.0
5
5 Page 
Si53313
2. Functional Description
The Si53313 is a low-jitter, low-skew dual 1:5 differential output buffer with an independent input for each bank.
The device has an any-format input that accepts most common differential or LVCMOS input signals. Each output
bank features control pins to select signal format, output enable, output divider setting and LVCMOS drive strength.
2.1. Universal, Any-Format Input
The Si53313 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including
LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various input ac- and dc-coupling
options supported by the device. Figures 3, 4, and 5 show the recommended input clock termination options.
Table 15. LVPECL, LVCMOS, and LVDS
1.8 V
2.5/3.3 V
LVPECL
AC-Couple DC-Couple
N/A N/A
Yes Yes
LVCMOS
AC-Couple DC-Couple
No No
No Yes
LVDS
AC-Couple DC-Couple
Yes No
Yes Yes
1.8 V
2.5/3.3 V
Table 16. HCSL and CML
HCSL
AC-Couple DC-Couple
CML
AC-Couple DC-Couple
No No Yes No
Yes Yes Yes No
0.1 µF
CLKx
Si53313
100
CLKx
0.1 µF
Figure 3. Differential LVPECL, LVDS, CML AC-Coupled Input Termination
VDDO = 3. 3 V or2. 5 V
CMOS
Driver
Rs
VDD
1 k
VDD
Si53313
Si53312
CLKx
50
CLKx
VTERM = VDD/2
1 k
VREF
Figure 4. LVCMOS DC-Coupled Input Termination
Rev. 1.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53313.PDF ] | |
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