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PDF SI53312 Data sheet ( Hoja de datos )
| Número de pieza | SI53312 | |
| Descripción | 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si53312
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX (<1.25 GHZ)
Features
10 differential or 20 LVCMOS outputs Low output-output skew: <70 ps
Ultra-low additive jitter: 45 fs rms Low propagation delay variation:
Wide frequency range:
<400 ps
dc to 1.25 GHz
Independent VDD and VDDO :
Any-format input with pin selectable 1.8/2.5/3.3 V
output formats: LVPECL, Low Power Excellent power supply noise
LVPECL, LVDS, CML, HCSL,
rejection (PSRR)
LVCMOS
Selectable LVCMOS drive strength to
2:1 mux with hot-swappable inputs
tailor jitter and EMI performance
Asynchronous output enable
Small size: 44-QFN (7 mm x 7 mm)
Output clock division: /1, /2, /4
(/2 and /4 for dc to 725 MHz)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 28.
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53312 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53312 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53312 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz
with guaranteed low additive jitter, low skew, and low propagation delay variability.
The Si53312 features minimal cross-talk and provides superior supply noise
rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Pin Assignments
Si53312
DIVA 1
SFOUTA[1] 2
SFOUTA[0] 3
Q2
Q2
GND
Q1
4
5
6
7
Q1 8
Q0 9
Q0 10
NC 11
GND
PAD
33 DIVB
32 SFOUTB[1]
31 SFOUTB[0]
30 Q7
29 Q7
28 NC
27 Q8
26 Q8
25 Q9
24 Q9
23 CLK_SEL
Patents pending
Functional Block Diagram
VREF
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
Vref
Generator
Power
Supply
Filtering
DivA
Switching
Logic
DivB
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Rev. 1.0 9/15
Copyright © 2015 by Silicon Laboratories
Si53312
1 page  
Si53312
Table 5. Output Characteristics (Low Power LVPECL)
(VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Output DC Common VCOM RL = 100 across Qn and Qn VDDOX – 1.895
Mode Voltage
Single-Ended
Output Swing
VSE RL = 100 across Qn and Qn
0.20
Typ
0.60
Max
Unit
VDDOX – 1.275 V
0.85 V
Table 6. Output Characteristics—CML
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Symbol
VSE
Test Condition
Terminated as shown in Figure 8
(CML termination).
Min
200
Typ Max Unit
400 550
mV
Table 7. Output Characteristics—LVDS
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(VDDO = 2.5 V or
3.3V)
Output Common
Mode Voltage
(VDDO = 1.8 V)
Symbol
VSE
VCOM1
VCOM2
Test Condition
RL = 100 Ω across QN and QN
VDDOX = 2.38 to 2.63 V, 2.97 to
3.63 V, RL = 100 Ω across QN
and QN
VDDOX = 1.71 to 1.89 V,
RL = 100 Ω across QN
and QN
Min
200
1.10
0.85
Typ Max
— 490
1.25 1.35
0.97 1.25
Unit
mV
V
V
Table 8. Output Characteristics—LVCMOS
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Output Voltage High
VOH
0.75 x VDDOX
—
—
Output Voltage Low
VOL
— — 0.25 x VDDOX
*Note: IOH and IOL per the Output Signal Format Table for specific VDDOX and SFOUTx settings.
Unit
V
V
Rev. 1.0
5
5 Page 
Si53312
2. Functional Description
The Si53312 is a low jitter, low skew 1:10 differential buffer with an integrated 2:1 input mux. The device has a
universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select
the active input clock. The selected clock input is routed to two independent banks of outputs. Each output bank
features control pins to select signal format, output enable, output divider setting and LVCMOS drive strength.
2.1. Universal, Any-Format Input
The Si53312 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including
LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various input ac- and dc-coupling
options supported by the device. Figures 3 and 4 show the recommended input clock termination options.
Table 15. LVPECL, LVCMOS, and LVDS
1.8 V
2.5/3.3 V
LVPECL
AC-Couple DC-Couple
N/A N/A
Yes Yes
LVCMOS
AC-Couple DC-Couple
No No
No Yes
LVDS
AC-Couple DC-Couple
Yes No
Yes Yes
1.8 V
2.5/3.3 V
Table 16. HCSL and CML
HCSL
AC-Couple DC-Couple
CML
AC-Couple DC-Couple
No No Yes No
Yes Yes (3.3 V) Yes
No
0.1 µF
CLKx
Si53312
100
/CLKx
0.1 µF
Figure 2. Differential LVPECL, LVDS, CML AC-Coupled Input Termination
VDDO = 3. 3 V or2. 5 V
CMOS
Driver
Rs
VDD
1 k
VDD
CLKx
50
CLKx
VTERM = VDD/2
1 k
VREF
Si53312
Figure 3. LVCMOS DC-Coupled Input Termination
Rev. 1.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53312.PDF ] | |
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