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PDF SI53365 Data sheet ( Hoja de datos )
| Número de pieza | SI53365 | |
| Descripción | 1:8 LOW JITTER CMOS CLOCK BUFFER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si53365
1:8 LOW JITTER CMOS CLOCK BUFFER (<200 MHZ)
Features
8 LVCMOS outputs
RoHS compliant, Pb-free
Low additive jitter: 125 fs rms typ Industrial temperature range:
Wide frequency range: 1 to 200 MHz –40 to +85 °C
Asynchronous output enable
Footprint-compatible with
Low output-output skew: <100 ps
CDCLVC1108
1.8, 2.5, or 3.3 V operation
16-TSSOP
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53365 is an ultra low jitter eight output LVCMOS buffer. The Si53365
utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from dc
to 200 MHz with guaranteed low additive jitter, low skew, and low propagation
delay variability. The Si53365 supports operation over the industrial temperature
range and can be operated from a 1.8 V, 2.5 V, or 3.3 V supply.
Functional Block Diagram
Ordering Information:
See page 9.
Pin Assignments
CLK 1
OE 2
Q0 3
GND 4
16 Q1
15 Q3
14 VDD
13 Q2
VDD 5
12 GND
VDD
Power
Supply
Filtering
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q4 6
GND 7
Q6 8
Patents pending
11 Q5
10 VDD
9 Q7
Q6
GND
Q7
OE
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si53365
1 page  
Si53365
Table 6. Thermal Conditions
Parameter
Thermal Resistance,
Junction to Ambient
Symbol
θJA
Test Condition
Still air
Value
124.4
Unit
°C/W
Table 7. Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Input Voltage
Symbol
TS
VDD
VIN
Test Condition
Min
–55
–0.5
–0.5
Typ Max
— 150
— 3.8
— VDD+
0.3
Unit
°C
V
V
Output Voltage
VOUT
— — VDD+ V
0.3
ESD Sensitivity
HBM
HBM, 100 pF, 1.5 kΩ
2000
—
—
V
ESD Sensitivity
CDM
500 — —
V
Peak Soldering Reflow TPEAK
Temperature
Pb-Free; Solder reflow profile
per JEDEC J-STD-020
—
— 260
°C
Maximum Junction
Temperature
TJ
— — 125 °C
Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Rev. 1.0
5
5 Page 
6. PCB Land Pattern
6.1. 16-TSSOP Package Land Pattern
Si53365
Figure 5. Si53365 16-TSSOP Package Land Pattern
Table 11. PCB Land Pattern
Dimension
Feature
(mm)
C1 Pad Column Spacing
5.80
E Pad Row Pitch
0.65
X1 Pad Width
0.45
Y1 Pad Length
1.40
Notes:
1. This Land Pattern Design is based on the IPC-7351
guidelines.
2. All feature sizes shown are at Maximum Material
Condition (MMC) and a card fabrication tolerance of
0.05 mm is assumed.
Rev. 1.0
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SI53365.PDF ] | |
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